Patents Examined by David X Yi
  • Patent number: 9875043
    Abstract: A method is used in managing data migration in storage systems. A request to migrate data of a logical object from a source storage pool to a destination storage pool is received. The data of the logical object is mapped to a mapped logical object created in the destination storage pool. The data of the logical object is relocated to storage space allocated in the destination storage pool. Mappings of the mapped logical object are updated to refer to the data relocated to the storage space allocated in the destination storage pool.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: January 23, 2018
    Assignee: EMC IP Holding Company, LLC.
    Inventor: Dayanand Suldhal
  • Patent number: 9870157
    Abstract: A data storage device includes a non-volatile semiconductor storage device and a controller that is configured to perform interleaving of small reads with large reads and small writes with large writes. In the example of reads, the controller receives a sequence of read commands including a first read command having a read size larger than a read threshold size and a second read command having a read size smaller than the read threshold size, and issue first and second read requests in succession to read data of a predetermined size less than the read threshold size, from the non-volatile semiconductor storage device. The interleaving is achieved by issuing the first read request to execute the first read command and the second read request to execute the second read command. As a result of this interleaving, the second read command will have a chance to complete earlier than the first read command even though it was received by the controller later in time.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: January 16, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Raja V. S. Halaharivi, Tony Chheang, Dishi Lai, Fred Au
  • Patent number: 9870289
    Abstract: A notifying system to notify a backup application of a backup key change includes receiving, from a backup application, a request to associate with a backup key, replicating the backup key to create a replica backup key, associating the replica backup key with the backup application, monitoring the backup key for a change, the change indicating a backup event has occurred, and setting the replica backup key to indicate the backup key has changed.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: January 16, 2018
    Assignee: CA, INC.
    Inventors: Umasankar Yallamraju, Subrahmanya Sarma Yellapragada, Vijaya Kumar Pothireddy, Ramakrishna Maddali
  • Patent number: 9864699
    Abstract: Aspects of the disclosure provide a circuit that includes a memory circuit and a controller circuit. The memory circuit is to have a look-up table (LUT) that associates logical address used in computation with physical address used in storage space. The LUT includes a first level LUT with first level entries corresponding to logical addresses, each first level entry includes an indicator field and a content field, and the indicator field is indicative of a compressible/non-compressible attribute of a physical address associated with a logical address. The controller circuit is to receive a logical address, and translate the logical address into a physical address associated with the logical address based on the LUT.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: January 9, 2018
    Assignee: Marvell International Ltd.
    Inventors: Wei Xu, Fei Sun, Ka-Ming Keung, Jinjin He, Young-Ta Wu, Tony Yoon
  • Patent number: 9864705
    Abstract: A method for switching between access methods while a data set is open includes attempting, on behalf of a first system, to gain access to a data set. The method further determines whether the data set is already open by a second system. In the event the data set is already open, the method uses a first access method to access the data set. In the event the data set is not already open, the method uses a second access method to access the data set. In certain embodiments, the first access method is an RLS (Record Level Sharing) access method and the second access method is a base VSAM (Virtual Storage Access Method) access method. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: November 1, 2015
    Date of Patent: January 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Neal E. Bohling, David C. Reed, Franklin E. McCune, Max D. Smith
  • Patent number: 9864519
    Abstract: Systems and methods are provided for performing write-with-response operations in a network on a chip architecture. In response to receiving an instruction to perform a write-with-response operation, a writer computing resource of a computing system (implemented using the network on a chip architecture) executes this instruction by performing a write operation for writing data to a memory location followed by a response operation for notifying a notification target computing resource of the computing system that the data has been written to the memory location.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: January 9, 2018
    Assignee: KnuEdge Incorporated
    Inventors: Doug Meyer, Jerry Coffin, Andy White
  • Patent number: 9864753
    Abstract: A data storage system tracks liability and insurance for an internal file system, liability being a number of slices needed to store file system data, insurance being a number of slices allowed to be consumed. A reserve of un-provisioned insurance is maintained from which slices are provisioned to the file system for use in storing file system data without immediate requirement for increasing the insurance. Slices are provisioned to the file system from the reserve of un-provisioned insurance based on a window criteria and a space criteria, the window criteria being that a number of free windows is less than a free window threshold, the space criteria being that a number of currently provisioned slices is less than a maximum allowed slices, which includes an overprovisioning factor applied to the primary file size to allow for growth of the primary file without immediate requirement for increasing provisioned insurance.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: January 9, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Philippe Armangau, Ahsan Rashid, Kumari Bijayalaxmi Nanda, Alexander Mathews
  • Patent number: 9857997
    Abstract: Provided are a computer program product, system, and method for replicating tracks from a first storage to a second and third storages. A determination is made of a track in the first storage to transfer to the second storage as part of a point-in-time copy relationship and of a stride of tracks including the target track. The stride of tracks including the target track is staged from the first storage to a cache according to the point-in-time copy relationship. The staged stride is destaged from the cache to the second storage. The stride in the cache is transferred to the third storage as part of a mirror copy relationship. The stride of tracks in the cache is demoted in response to destaging the stride of the tracks in the cache to the second storage and transferring the stride of tracks in the cache to the third storage.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Benhase, Lokesh M. Gupta, Brian D. Hatfield, Gail A. Spear
  • Patent number: 9858180
    Abstract: A storage controller receives a request to establish a point-in-time copy operation by placing a space efficient source volume in a point-in-time copy relationship with a space efficient target volume, wherein subsequent to being established the point-in-time copy operation is configurable to consistently copy the space efficient source volume to the space efficient target volume at a point in time. A determination is made as to whether any track of an extent is staging into a cache from the space efficient target volume or destaging from the cache to the space efficient target volume. In response to a determination that at least one track of the extent is staging into the cache from the space efficient target volume or destaging from the cache to the space efficient target volume, release of the extent from the space efficient target volume is avoided.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Theresa M. Brown, Ellen J. Grusy, Lokesh M. Gupta, Brian D. Hatfield, Kurt A. Lovrien, Carol S. Mellgren, Raul E. Saba
  • Patent number: 9858000
    Abstract: A sustained status accelerating method for a storage device includes: controlling the storage device to receive a sustained status command from the outside; and controlling the storage device to enter the sustained status using a sustained valid page count (SVPC) table in response to the sustained status command so that each of a plurality of blocks constituting the storage device has a value greater than a predetermined valid page count. The SVPC table includes a valid page count with respect to each of the blocks in the storage device.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: January 2, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su-Gon Kim, Sangyong Lee, Dongbin Park, Chanik Park
  • Patent number: 9858073
    Abstract: The present application provides a method of randomly accessing a compressed structure in memory without the need for retrieving and decompressing the entire compressed structure.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: January 2, 2018
    Assignee: LINEAR ALGEBRA TECHNOLOGIES LIMITED
    Inventor: David Maloney
  • Patent number: 9852021
    Abstract: Provided are a method and apparatus for method and apparatus for encoding registers in a memory module. A mode register command is sent to the memory module over a bus, initialization of the memory module before the bus to the memory module is trained for bus operations, to program one of a plurality of mode registers in the memory module, wherein the mode register command indicates one of the mode registers and includes data for the indicated mode register.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: December 26, 2017
    Assignee: INTEL CORPORATION
    Inventors: Bill Nale, John V. Lovelace, Murugasamy M. Nachimuthu, Tuan M. Quach
  • Patent number: 9847122
    Abstract: A program method of a multi-bit memory device is provided. First page data is programmed in a first region of a memory cell array. The first page data is stored in a first buffer of a page buffer. Second page data is programmed in the first region of the memory cell array. The second page data is stored in a third buffer of the page buffer. Third page data is stored in the first region of the memory cell array. The second page data stored in the third buffer is transferred to a second buffer of the page buffer and the third page data is stored in the third buffer. The first to third page data stored in page buffer are programmed in a second region of the memory cell array.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: December 19, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wan-Soo Choi, Taec-Jun Kim, Sang-Wook Nam, Jae-Hwa Lee
  • Patent number: 9842630
    Abstract: A memory component includes a memory bank comprising a plurality of storage cells and a data interface block configured to transfer data between the memory component and a component external to the memory component. The memory component further includes a plurality of column interface buses coupled between the memory bank and the data interface block, wherein a first column interface bus of the plurality of column interface buses is configured to transfer data between a first storage cell of the plurality of storage cells and the data interface block during a first access operation and wherein a second column interface bus of the plurality of column interface buses is configured to transfer the data between the first storage cell and the data interface block during a second access operation.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: December 12, 2017
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern
  • Patent number: 9842054
    Abstract: In a method for processing cache data of a computing device, a storage space of the storage device is divided into sections, and a section number of each data block in the storage device is determined according one of the sections in the storage device which each data block belongs to. A field is added for each data block in the storage device to record a section number of each data block in the storage device. When the cache data in the cache memory requires to be written back to the storage device, cache data with the section number is searched from all of the cache data in the cache memory to be written back to a corresponding section in the storage device.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: December 12, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chun-Hsieh Chiu, Hsiang-Ting Cheng
  • Patent number: 9842009
    Abstract: A method is provided for detecting a race condition of a parallel task when accessing a shared resource in a multi-core processing system. The method requires that a core requires only a read access to the data set of another core, thereby ensuring better decoupling of the tasks. In an initialisation phase, initial values of global variables are assigned, in an activation phase, each core determines if the other core has written new values to the variables and if so, detects a race condition. Initial values are restored for each variable in a deactivation phase.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: December 12, 2017
    Assignee: NXP USA, Inc.
    Inventor: Oleksandr Sakada
  • Patent number: 9842032
    Abstract: The subject matter of this specification can be implemented in, among other things, a method including receiving a request to create a live snapshot of a state of a virtual machine including a memory and an original disk file. The method further includes copying, by a hypervisor, data from the memory to a storage device to form a memory snapshot. The method further includes pausing the virtual machine and creating a new disk file at a reference point-in-time. The original disk file is a backing file of the new disk file. The method further includes resuming the virtual machine. The virtual machine is to perform disk operations using the new disk file after the reference point-in-time. The method further includes copying the original disk file to a disk snapshot file. The method further includes providing the live snapshot including the disk snapshot file and the memory snapshot.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: December 12, 2017
    Assignee: Red Hat, Inc.
    Inventor: Eric Blake
  • Patent number: 9841926
    Abstract: According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: December 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair
  • Patent number: 9836108
    Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: December 5, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihisa Kojima, Katsuhiko Ueki
  • Patent number: 9823976
    Abstract: Techniques to back up data are disclosed. In various embodiments, a copy of a free block map as of a first time associated with a first backup is stored in persistent data storage. Writes made subsequent to the first backup to blocks not listed as free in the copy of the free block map as of the first time are tracked in a persistently-stored change block tracking log. A free block map as of a second time and the previously-stored copy of the free block map as of the first time are used to determine which blocks listed as free in the free block map as of the first time have been written to since the first time. At least a subset of blocks determined to have been written to since the first time are including in an incremental backup.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: November 21, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Kedar Shrikrishna Patwardhan, Anand Shrikrishna Ghatnekar