Patents Examined by David X Yi
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Patent number: 9933950Abstract: Apparatuses, systems, methods, and computer program products are disclosed for interrupting storage operations. A frequency module is configured to determine a frequency for pausing a storage operation. An interrupt module is configured to pause execution of a storage operation according to a determined frequency. A resume module is configured to continue a paused storage operation in response to a trigger.Type: GrantFiled: March 12, 2015Date of Patent: April 3, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Jea Hyun, James Peterson, Long Pham, John Strasser, Hairong Sun, Kapil Verma
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Patent number: 9934231Abstract: Implementations described and claimed herein provide a system and methods for prioritizing data in a cache. In one implementation, a priority level, such as critical, high, and normal, is assigned to cached data. The priority level dictates how long the data is cached and consequently, the order in which the data is evicted from the cache memory. Data assigned a priority level of critical will be resident in cache memory unless heavy memory pressure causes the system to reclaim memory and all data assigned a priority state of high or normal has been evicted. High priority data is cached longer than normal priority data, with normal priority data being evicted first. Accordingly, important data assigned a priority level of critical, such as a deduplication table, is kept resident in cache memory at the expense of other data, regardless of the frequency or recency of use of the data.Type: GrantFiled: December 22, 2014Date of Patent: April 3, 2018Assignee: Oracle International CorporationInventors: Mark Maybee, Lisa Week
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Patent number: 9927989Abstract: A method for storing data includes establishing an extended generation group comprising a plurality of data sets. The plurality of data sets include a first data set containing primary members and a first number of generations of each of the primary members, and a second data set containing a second number of generations of each of the primary members. The first data set and the second data set are stored on different tiers of a tiered storage system, and may even be stored on different volumes. The first data set may be stored on higher performance storage media and the second data set may be stored on lower performance storage media. Additionally, the second number will typically be greater than the first number so that more generations are stored on lower performance storage media. A corresponding system and computer program product are also disclosed.Type: GrantFiled: November 1, 2015Date of Patent: March 27, 2018Assignee: International Business Machines CorporationInventors: Derek L. Erdmann, David C. Reed, Thomas C. Reed, Max D. Smith
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Patent number: 9927999Abstract: A storage device may include a data storage portion, including a plurality of blocks of data, and a controller. The controller may be configured to receive a command that includes an inherent trim request for the plurality of blocks of data. The controller may be configured to perform a trim operation on a first set of trim blocks from the plurality of blocks of data, which may include fewer than all blocks of the plurality of blocks of data and may include trim blocks on which the controller can complete the trim operation within a predetermined time. The controller may be configured to update a pending trim table to include an indication of a second set of trim blocks on which trim is to be performed, which may include blocks of data on which the controller cannot complete the trim operation within the predetermined time.Type: GrantFiled: September 9, 2016Date of Patent: March 27, 2018Assignee: Western Digital Technologies, Inc.Inventors: Darin Edward Gerhart, Timothy Glen Hallett, Daniel Robert Lipps, Nicholas Edward Ortmeier
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Patent number: 9927982Abstract: A computer program product includes a computer readable storage medium having program instructions executable by a tape drive to cause the tape drive to perform a method comprising: receiving, at the tape drive, a request for a write operation to be performed in the tape drive; determining, by the tape drive, an expected transaction size of a next write operation; comparing, by the tape drive, the expected transaction size of the next write operation to each of a first transaction size threshold and a second transaction size threshold in response to receiving the request; determining, by the tape drive, an optimum a write procedure based at least in part on the comparison; and invoking, by the tape drive, the optimum write procedure in response to determining the optimum write procedure.Type: GrantFiled: August 18, 2017Date of Patent: March 27, 2018Assignee: International Business Machines CorporationInventors: James M. Karp, Takashi Katagiri, Yuhko Mori, Yutaka Oishi
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Patent number: 9910591Abstract: The disclosed embodiments provide a system that facilitates the execution of a software program. During operation, the system obtains a memory layout for an object instance in a software program, wherein the memory layout includes a set of offsets and a set of allocated sizes of a set of components associated with the object instance. Next, the system uses the memory layout to determine a first memory space occupied by data in the object instance and a second memory space occupied by padding in the object instance. The system then displays a visualization of the memory layout on the computer system, wherein the visualization includes a first graphical distinction between the first memory space and the second memory space.Type: GrantFiled: November 5, 2014Date of Patent: March 6, 2018Assignee: Oracle International CorporationInventors: Jean-Francois Denise, Steven J. Drach, Charles J. Hunt
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Patent number: 9898419Abstract: For a cache in which a plurality of frequently accessed data segments are temporarily stored, reference count information of the plurality of data segments, in conjunction with least recently used (LRU) information, is used to determine a length of time to retain the plurality of data segments in the cache according to a predetermined weight, where notwithstanding the LRU information, those of the plurality of data segments having a higher reference counts are retained longer than those having lower reference counts.Type: GrantFiled: May 19, 2017Date of Patent: February 20, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joseph S. Hyde, II, Subhojit Roy
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Patent number: 9898224Abstract: When migrating data, a first message is received at a target data storage system from a source data storage system. The target data storage system includes a data storage optimizer that performs automated data movement optimizations. The first message requests a reservation of a first amount of storage on a first storage tier for performing a data migration to migrate data from the source to the target data storage system. A first capacity limit of the first storage tier is reduced by the first amount thereby representing the reservation of the first amount of storage for performing the data migration. If the first storage tier does not include an amount of available storage of at least the first amount, processing is performed to increase the amount of available storage of the first storage tier.Type: GrantFiled: September 12, 2012Date of Patent: February 20, 2018Assignee: EMC IP Holding Company LLCInventors: Marik Marshak, Hui Wang, Xiaomei Liu, Sean C. Dolan, Alexandr Veprinsky
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Patent number: 9898210Abstract: A method, and system for implementing enhanced fast full synchronization for remote disk mirroring in a computer system. A source backup copy is made locally available to a target for remote disk mirroring. Sectors are identified that are different between the source and target. A hash function is used over a block to be compared, with an adaptive number of tracking sectors per block, starting with a minimum block size.Type: GrantFiled: July 26, 2016Date of Patent: February 20, 2018Assignee: International Business Machines CorporationInventors: Aaron T. Albertson, Robert Miller, Brian A. Nordland, Kiswanto Thayib
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Patent number: 9899088Abstract: Circuits and methods are disclosed for decomposition of a content addressable memory into a plurality of CAMs having a lower cost. In an example implementation, a set of CAM rules are grouped into a plurality of subsets. For each of the subsets, CAM rules in the subset are reformatted for storage in a respective CAM configured to store fewer ternary bits or configured for prefix match. Each reformatted subset of CAM rules are stored in the respective CAM. A search key formatting circuit is configured to reformat an input search key for each of the respective CAMs is used to store the reformatted subsets to produce a respective reformatted search key and input the respective reformatted search key to the respective CAM.Type: GrantFiled: September 23, 2015Date of Patent: February 20, 2018Assignee: XILINX, INC.Inventor: Weirong Jiang
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Patent number: 9891846Abstract: An information handling system a first controller and a solid state drive. The first controller receives an indication that a forced shutdown of the information handling system has been initiated, and triggers a cache flush command in response to receiving the indication that the forced shutdown has been initiated. The solid state drive includes a memory to store data, a cache to buffer data prior to writing the data in the memory, and a second controller. The second controller receives the cache flush command, and flushes the cache by writing the data in the cache to the memory in response to the cache flush command being received.Type: GrantFiled: March 31, 2015Date of Patent: February 13, 2018Assignee: DELL PRODUCTS, LPInventors: Isaac Hsu, Adolfo S. Montero
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Patent number: 9892041Abstract: Various methods and systems for optimizing cache consistency are disclosed. For example, one method involves writing data to a file during a write transaction. The file is stored in a persistent storage device and cached in a non-volatile storage device. The method determines if an in-memory flag associated with the persistent storage device set. If the in-memory flag is not set, the method increases a generation count associated with the persistent storage device before a write transaction is performed on the file. The method then sets the in-memory flag before performing the write transaction on the file. In other examples, the method involves using a persistent flag associated with the non-volatile storage device to maintain cache consistency during a data freeze related to the taking of a snapshot by synchronizing generation counts associated with the persistent storage device and the non-volatile storage device.Type: GrantFiled: September 30, 2014Date of Patent: February 13, 2018Assignee: Veritas Technologies LLCInventors: Anindya Banerjee, Ryan Lefevre
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Patent number: 9886389Abstract: This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core bypasses immediate cache memory units with low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.Type: GrantFiled: November 21, 2008Date of Patent: February 6, 2018Assignee: International Business Machines CorporationInventors: Dan P. Dumarot, Karl J. Duvalsaint, Daeik Kim, Moon J. Kim, Eugene B. Risi
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Patent number: 9886285Abstract: Systems and methods are disclosed for executing firmware in a computing device. A computing device comprises a controller comprising an interface and an interface state machine, non-volatile storage coupled to the interface state machine, the non-volatile storage storing initialization parameters, and a non-volatile memory module storing firmware for the device, the memory module coupled to the controller via the interface. The controller is configured to initialize the interface using the initialization parameters and the interface state machine, train the interface using the initialization parameters and the interface state machine, and execute the firmware from the non-volatile memory module.Type: GrantFiled: March 31, 2015Date of Patent: February 6, 2018Assignee: Western Digital Technologies, Inc.Inventors: Dean Mitcham Jenkins, Dale C. Main
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Patent number: 9880946Abstract: Described are data replication techniques. Y cycles of writes directed to a first storage device of a first data storage system are collected, Y>2. Each of the Y cycles denotes writes directed to the first storage device at an occurrence of a fixed time interval. Writes of cycle N?1 directed to the first storage device are transmitted from the first data storage system to a second data storage system. Writes of cycle N?2 are applied to a second storage device. An acknowledgement regarding cycle N?1 is sent from the second data storage system to the first data storage system responsive to determining that the writes of cycle N?1 directed to the first storage device have been received by the second data storage system and that the writes of cycle N?2 directed to the first storage device have been applied to the second storage device.Type: GrantFiled: June 30, 2015Date of Patent: January 30, 2018Assignee: EMC IP Holdings Company LLCInventors: Benjamin Yoder, Bhaskar Bora
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Patent number: 9880904Abstract: Supporting multiple backup applications using a single change tracker includes receiving, from a backup application, a request to associate with a backup map, replicating the backup map to create a replica backup map associated with the backup application, and updating the replica backup map based on changes in the backup map.Type: GrantFiled: December 12, 2014Date of Patent: January 30, 2018Assignee: CA, INC.Inventors: Umasankar Yallamraju, Subrahmanya Sarma Yellapragada, Vijaya Kumar Pothireddy, Ramakrishna Maddali
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Patent number: 9875044Abstract: A method is provided for operating a data storage device capable of compensating for an initial threshold voltage shift of multiple memory cells. The method includes generating a first compression value for a first write address corresponding to a first write request input during a first time interval among different time intervals, and storing the first compression value in a first table among multiple tables.Type: GrantFiled: July 16, 2015Date of Patent: January 23, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Dong Hwan Lee, Jun Jin Kong, Chang Kyu Seol, Hong Rak Son
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Patent number: 9875186Abstract: The present technology relates to managing data caching in processing nodes of a massively parallel processing (MPP) database system. A directory is maintained that includes a list and a storage location of the data pages in the MPP database system. Memory usage is monitored in processing nodes by exchanging memory usage information with each other. Each of the processing nodes manages a list and a corresponding amount of available memory in each of the processing nodes based on the memory usage information. Data pages are read from a memory of the processing nodes in response to receiving a request to fetch the data pages, and a remote memory manager is queried for available memory in each of the processing nodes in response to receiving the request. The data pages are distributed to the memory of the processing nodes having sufficient space available for storage during data processing.Type: GrantFiled: July 8, 2015Date of Patent: January 23, 2018Assignee: FutureWei Technologies, Inc.Inventors: Huaizhi Li, Qingqing Zhou, Guogen Zhang
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Patent number: 9875049Abstract: A memory system and method for reducing peak current consumption. In one embodiment, a method is provided that is performed in a memory system comprising a memory with a plurality of blocks, wherein each block has a peak current consumption. In this method, a plurality of metablocks is created, wherein each metablock is created by grouping together blocks with complementary peak current consumption. Next, the metablocks are programmed. Because each of the metablocks has blocks with complementary peak current consumption, each of the metablocks has similar peak current consumption when programmed. Other embodiments are provided.Type: GrantFiled: August 24, 2015Date of Patent: January 23, 2018Assignee: SanDisk Technologies LLCInventors: Eran Erez, Jonathan H. Hsu, Ken Q. Nguyen
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Patent number: 9875047Abstract: Embodiments of the present disclosure enable exit-less host memory locking in a virtualized environment. An example method comprises protecting, by a processing device of a host computer system, a memory page from being accessed by a guest operating system of a virtual machine running on the host computer system. The locking indicator resides in a shared memory accessible by the guest operating system. Responsive to determining that the locking indicator indicates that the memory page is not in a locked state, the memory page is accessed. Thereafter, access to the memory page is re-enabled for the guest operating system.Type: GrantFiled: May 27, 2015Date of Patent: January 23, 2018Assignee: Red Hat Israel, Ltd.Inventors: Michael Tsirkin, Andrea Arcangeli