Abstract: A first write transaction is received by a device that includes a transaction identifier and a memory location identifier. The memory location identifies a register or a memory location of a device. A value from the register or memory location is read. A second write transaction is sent to a block of host memory. The second write transaction includes the value and the transaction identifier.

Abstract: Described is an I3C Repeater. The I3C Repeater may have a first circuitry with an I3C interface, a second circuitry with an I2C interface, and a datapath circuitry coupled to the first circuitry and the second circuitry. The second circuitry may be operable to convert a transaction received on the I2C interface into a transaction for the I3C interface, and to convert a transaction received on the I3C interface into a transaction for the I2C interface. The I3C Repeater may also have additional circuitries operable to convert transactions received on one of an SPI interface, a UART interface, and a Debug bus interface into transactions for the I3C interface, and vice-versa.

Abstract: A portable patient-care kit is disclosed. The kit includes two-housing portions, a plurality of compartments, a touch-screen user interface device, and a light bar. The two-housing portions pivotally coupled together to form a container space. The plurality of compartments is disposed within at least one of the housing portions such that each compartment is configured to retain at least one medical apparatus. The touch-screen user interface device has a transceiver that can communicate via a mobile data network. The light bar is disposed along an exterior of one of the two-housing portions configured provide light.

Abstract: The present disclosure discloses a communication method for a slave device connected to a master device via an I2C bus. The method includes detecting the condition of a byte end flag when the slave device is in a transmission mode, and clearing the byte end flag to stop transmitting data to the master device as the slave device is in the transmission mode when the byte end flag is detected to be in a first condition. The first condition indicates all data requested by the master device has been transmitted by the slave device. The present disclosure further discloses a slave device using the above-mentioned communication method. When the slave device is in the transmission mode, it is unnecessary to switch the operation mode of the slave device to stop the slave device from continuing transmitting data when the last byte of data has been transmitted.

Abstract: Improvements over existing data collection interfaces disclosed herein include, among other things, additional logic blocks (and associated timers, state machines, and registers) to off-load data collection and data processing prior to waking a microprocessor from a sleep mode. For example, an improved data collection interface collects a predetermined number of sensor values from a sensor while maintaining active a single communication session with the sensor over a pin of the interface. The microprocessor remains in the sleep mode for an entire duration of the single communication session. The data collection interface can reduce the likelihood of false starts of the microprocessor by using the logic blocks to verify that data meet preconditions prior to interrupting the microprocessor. The data collection interface can reduce the overall power consumption of a chip in which the microprocessor is integrated by a factor of at least about 2× (i.e., 50% reduction in power consumption).

Abstract: Methods and systems for a networked computing system are provided. One method includes generating, based on a first topology, a first proxy endpoint by a first device of a first pluggable compute module; establishing a communication tunnel between the first proxy endpoint and a non-volatile memory express (NVMe) storage device for peer-to-peer communication between the first proxy endpoint of the first device and a controller of the NVMe storage device. An NVMe translation module receives a request for the NVMe storage device from the first proxy endpoint and the NVMe translation module translates the request to an NVMe request for the NVMe storage device for accessing storage space at the NVMe storage device. The method further includes de-allocating the first proxy endpoint, when the first topology is deactivated making the first pluggable compute module and the NVMe storage device available for a second topology.

Abstract: A method and apparatus for providing power state information using in-band signaling are described. In one embodiment, an integrated circuit (IC) device comprises a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; and control logic operable to obtain data for inclusion in a response to the command, wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC.

Abstract: Some examples can enable virtual bridges to be hot plugged into a virtual Peripheral Component Interconnect (vPCI) system. For example, a number of subordinate buses that are connected to a vPCI bridge in the vPCI system can be determined. The vPCI system can be for a virtual machine. A parameter value can then be generated by adding an integer to the number of subordinate buses that are connected to the vPCI bridge. The integer can be a predefined number of additional subordinate buses to enable to be connected to the vPCI bridge. The parameter value can then be assigned to the vPCI bridge. This may enable additional virtual bridges to be hot plugged into the vPCI system at a later time. For example, a new virtual bridge can be added to the vPCI system using the parameter value for the vPCI bridge.

Abstract: An information handling system includes a processor configured to write a first command stride and a second command stride. Each of the first command stride and the second command stride includes logical commands in a single queue, and each of the logical commands is mapped for processing by a peripheral component interconnect express (PCIe). An accelerator may perform a logical separation of the logical commands based on the mapping of each logical command, wherein the logical commands are processed in parallel by the PCIe drives.

Abstract: Apparatus for communications includes a CPU, a system memory, and a network interface controller (NIC), which is configured to receive incoming data packets from a network, to post the received data packets in a designated queue for delivery to the CPU. The NIC issues interrupts to the CPU in response to the incoming data packets at a rate determined, for the designated queue, in accordance with an interrupt moderation parameter that is set for the queue. During each of a succession of monitoring periods, the CPU measures for the designated queue a current throughput of the incoming data packets and a current rate of interrupts, makes a comparison between the current measured throughput and rate of interrupts to the throughput and rate of interrupts that were measured during a preceding period in the succession, and selects and applies an update to the interrupt moderation parameter responsively to the comparison.

Abstract: An electronic apparatus is provided. The electronic apparatus includes a first integrated circuit (IC) and a second IC. The direction pin of the first IC outputs a direction control signal to the direction pin of the second IC. The first IC takes a control right when the direction control signal is in a first logic state. The clock pin of the first IC outputs a first clock signal to the clock pin of the second IC when the first IC takes the control right. The second IC takes the control right when the direction control signal is in a second logic state. The clock pin of the second IC outputs a second clock signal to the clock pin of the first IC when the second IC takes the control right.

Abstract: A plurality of transfer modules (402-0 to 402-M) that transfer data between processing units are provided so as to respectively correspond to a plurality of processing units (401-0 to 401-M). First ring buses (403-0 to 403-M) connect, for each of the processing units (401-0 to 401-M), subunits within a corresponding processing unit and the transfer module corresponding to the processing unit so that they form a ring shape. The plurality of transfer modules (402-0 to 402-M) are connected so that they form a ring shape by a second ring bus (404).

Abstract: Provided are a system and method for combining USB data streams. In one example, the method may include receiving, via an input port, a first universal serial bus (USB) input signal from a first device that is connected to the input port, receiving, via an interface, a second USB input signal from a second device, combining data from the first USB input signal and data from the second USB input signal to generate a combined USB data signal, and outputting, via an output port, the combined USB data signal to a third device that is connected to the output port. The system and method described herein can improve USB data transfer by combining USB data from multiple USB streams into a single USB output stream.

Abstract: A message bus-based streaming rules engine is disclosed. In various embodiments, a data analysis system as disclosed herein includes a communication interface configured to receive log data; and a processor coupled to the communication interface and configured to: parse the log data to generate a data unit comprising a data value; and send the data unit via a message bus to a rule actor configured to apply a rule based at least in part on the data value.

Abstract: Embodiments presented herein provide for hot swappable connections to various storage devices. In one embodiment, a storage controller includes an interface operable to connect to at least one of a storage device and a midplane connected to a plurality of Non Volatile Memory Express (NVMe) storage devices. The storage controller also includes a processor operable to detect when the interface is connected to the mid-plane, to determine that the NVMe storage devices each have a x4 NVMe connection, and to communicate sideband signaling, including a reference clock, to the NVMe storage devices through the midplane via Inter-Integrated Circuit (I2C) upon determining that the NVMe storage devices each have a x4 NVMe connection.

Abstract: Methods of accessing hardware input/output (I/O) queues by software threads performing operations on a storage system, such as a filesystem, are described herein. In one embodiment, a method for performing I/O operations on a filesystem stored at least in part on a storage device involves creating a channel to map exclusively to one hardware I/O queue of the storage device. The channel includes an instance of a software primitive in the filesystem to route I/O requests to access objects in the filesystem from an application executing on one or more threads to the one hardware I/O queue to which the channel maps. The method also involves submitting the I/O requests to access the objects in the filesystem from at most one thread of the application at a given time to the one hardware I/O queue using the channel.

Abstract: A write blocking system may include a host computer. The host computer may include a host processor configured as a blocking driver. A separate connection interface device may be is configured to be operatively coupled to the host computer, and include a drive socket and a processor assembly. The drive socket may be connected to a storage drive. The processor assembly may communicate with the blocking driver while the connection interface device is operatively coupled to the host computer. The processor assembly may selectively establish communication between the storage drive and the host computer after communication between the processor assembly and the blocking driver. The blocking driver may prevent the host computer from altering data stored on the connected storage drive.

Abstract: A method for updating software in a computer system, comprising at least a central processor and multiple adapter cards, wherein the adapter cards are attached to a network, the method comprising (i) the central processor generating a distribution map based on configuration data of the network (100); (ii) the central processor sending the software update data and the distribution map to a receiving adapter card of the adapter cards; (iii) in response to receiving the software update data and the distribution map, the receiving adapter card applying the received software update data and creating at least one modified distribution map.

Abstract: A system for chassis management includes a plurality of motherboards of a chassis, a plurality of baseboard management controllers (BMCs), and at least one chassis level component. Each of the plurality of BMCs is associated with one of the plurality of motherboards. The plurality of BMCs are interconnected via a first communication bus. The plurality of BMCs and the at least one chassis level component are interconnected via a second communication bus. One BMC of the plurality of BMCs is configured to operate as a virtual chassis management controller (VCMC) for the chassis. The VCMC is configured to exchange data with other BMCs of the plurality of BMCs over the first communication bus and manage the at least one chassis level component over the second communication bus.

Abstract: A processor includes a core and an interrupt controller. The interrupt controller includes logic to read interrupt data from a memory, the interrupt data including a timestamp, an allowable delay value, and at least one interrupt vector. The interrupt controller also includes a delay-comparison circuit to determine a time lapse based on the timestamp and a system clock signal and to compare the time lapse to the allowable delay value. Further, the interrupt controller includes a second logic to determine whether to invoke an interrupt handler based on the comparison of the time lapse to the allowable delay value.