Abstract: A memory controller circuit coupled to multiple memory circuits may receive a read request for a particular one of the memory circuits and insert the read request into one of multiple linked lists that includes a linked list whose entries correspond to previously received read requests and are linked according to respective ages of the read requests. The memory controller circuit may schedule the read request using a head pointer of one of the multiple linked lists.

Abstract: A first write transaction is received by a device that includes a transaction identifier and a memory location identifier. The memory location identifies a register or a memory location of a device. A value from the register or memory location is read. A second write transaction is sent to a block of host memory. The second write transaction includes the value and the transaction identifier.

Abstract: A communication system capable of shortening a setting time of an ID and reducing an incorrect setting is provided. A master device, when receiving an ID assignment request from a writing device, turns on all a plurality of semiconductor relays, and after a predetermined time has elapsed, turns all off, sequentially turns on the semiconductor relays and each time turning on the semiconductor relays, sends the corresponding ID. The plurality of slave devices, when receiving the ID assignment request from the writing device after supplying power, stores the fact in the ID request area, waits for a reception of the ID from the master device without confirming reception of the ID assignment request, and sets the ID as its own ID if determining that the ID assignment request has already been received by the ID request area after power is supplied.

Abstract: Logic on the baseboard can be used to provide backfeed protection by determining the condition of the peripheral component before enabling communication over a data cable to the peripheral component. By determining the condition of the peripheral component prior to beginning communications, the baseboard can reduce the likelihood that the baseboard asserts a wire on the data cable before the peripheral component receives power. With such information available to the baseboard, the baseboard avoids supplying a data signal over a wire of the data cable that would cause the destination circuitry of the peripheral component from exceeding its safety specification. When a bias voltage exists on the wire of the data connector corresponding to the peripheral component, the peripheral component is considered powered-on and data can be communicated to the peripheral component.

Abstract: A communication device perform operations includes: receiving, from a management device, a first management request which is a request for first status information; receiving, from the management device, a second management request which is a new request for the first status information; determining a transmission timing by using a first period between a reception timing of the first management request and a reception timing of the second management request, the transmission timing being a timing of transmitting to the function executing device a first status request for inquiring about the first status information through the second communication interface; and receiving, from the function executing device, information including the first status information in response to the first status request being transmitted to the function executing device through the second type communication interface in accordance with the determined transmission timing.

Abstract: An embodiment of a semiconductor apparatus may include technology to detect a collision for a read request of an electronic storage device, and read data for the read request directly from a transfer buffer if the collision is detected. Other embodiments are disclosed and claimed.

Abstract: A write blocking system may include a host computer. The host computer may include a host processor configured as a blocking driver. A separate connection interface device may be is configured to be operatively coupled to the host computer, and include a switch and a connection interface control device, such as a processor assembly. The switch may be connected by the drive socket to a storage drive. The connection interface control device may communicate with the blocking driver while the connection interface control device is operatively coupled to the host computer. The connection interface control device may selectively establish communication between the storage drive and the host computer by operating the switch after communication between the connection interface control device and the blocking driver. The blocking driver may prevent the host computer from altering data stored on the connected storage drive.

Abstract: A hardware independent peripheral control system and method are disclosed. The system comprises: a virtualised controller (20) executable by a processor (35) of a host system (30). The virtualised controller (20), when executed by the host system (30), has an input interface (21), an output interface (22), a processor (23) and a memory (24). The memory (24) encodes data on one or more peripheral specific instructions to control a peripheral (40) attached or connected to the host system (30). The input interface (21) is configured to receive peripheral agnostic instructions from the host system (30).

Abstract: A peripheral module of a programmable controller and method for operating the peripheral module, wherein in a calibration mode a base voltage value is supplied by the peripheral module to a terminal via a switching device, the supply potential is changed at a start time by the peripheral module to the modified value and a response time at which the expected change occurs is acquired, and the valid time interval is ascertained by the peripheral module utilizing the start time and the response time.

Abstract: A method for handling a command ID conflict in an NVMe-based solid-state drive (SSD) device includes fetching, from a host submission queue (HSQ), one or more commands submitted by a host device. The fetched commands are checked to determine if there is a command ID conflict. A command ID (CID) error interrupt is communicated to firmware of the SSD device if the command ID conflict is detected. A command validation is performed for the one or more commands on receiving the CID error interrupts. A command response is communicated with additional special information from the device FW to the host device for a command having a command ID conflict. One or more resources associated with the one or more commands are released based on the command response.

Abstract: Redirection of USB devices in nested hub environments can be supported. A redirection driver can detect when a USB device has been connected to the internal USB hub of a client terminal. Based on the type of the USB device, the redirection driver can selectively attach a filter device object to a physical device object for the USB device. Additionally, when a functional device object is loaded, the redirection driver can selectively attach a filter device object to the functional device object based on whether the functional device object represents a USB device that is registered as a USB hub. This selective loading of filter device objects ensures that a USB device connected to an external USB hub can be redirected while also maintaining the ability to redirect simple USB devices and USB composite devices with and without interface level redirection.

Abstract: A plurality of system on chips (SoCs) in a server computer can be coupled to a plurality of memory agents (MAs) via respective Serializer/Deserializer (SerDes) interfaces. Each of the plurality of MAs can include one or more memory controllers to communicate with a memory coupled to the respective MA, and globally addressable by each of the SoCs. Each of the plurality of SoCs can access the memory coupled to any of the MAs in uniform number of hops using the respective SerDes interfaces. Different types of memories, e.g., volatile memory, persistent memory, can be supported.

Abstract: Technologies for data processing or computation on data storage devices include a data storage controller. The data storage controller is configured to receive a data request from a compute device, determine an input data range specified by the compute device to be processed in the data storage device without sending data located at the input data to the compute device, read input data from the input data range, perform a data operation on the input data specified by the compute device to generate output data, and write the output data to an output data range specified by the compute device.

Abstract: A differential pair contact resistance asymmetry compensation system includes a differential trace pair that is provided on a board, a transmitter device that is coupled to the differential trace pair via a transmitter device connector interface, and a receiver device that is coupled to the differential trace pair via a receiver device connector interface. The receiver device receives, from the transmitter device via the differential trace pair, a contact resistance compensation data stream. The receiver device adjusts an impedance provided by the receiver device to compensate for a contact resistance asymmetry in at least the receiver device connector interface, and sets the impedance provided by the receiver device.

Abstract: A system and method for multi-channel communication with dual in-line memory modules (“DIMMs”) is disclosed. The system retrieves information characterizing a plurality of memory channels, each of each is configurable to facilitate data communication between a DIMM and a memory controller with associated memory channel interfaces. Based on the retrieved information, one of the memory channels is designated as the active memory channel, granting the designated memory channel the ability to issue memory requests or transactions to the DIMM. On a periodic or as-needed basis (e.g., when the active memory channel is stalled or nearly stalled), the system determines whether to designate a different of the memory channels as the active memory channel, thereby enabling the newly-designated active memory channel the ability to issue memory requests or transactions to the DIMM. In some embodiments, only one of the memory channels is active at a time for communication with each DIMM.

Abstract: An integrated circuit comprising a plurality of one-hot-bit multiplexers interconnected to form a switch interconnect network (e.g., hierarchical and/or mesh type networks), wherein each of the plurality of one-hot-bit multiplexers includes an output, inputs, and input selects, wherein each one-hot-bit multiplexer of the plurality of one-hot-bit multiplexers are capable of receiving: (i) an input select signal to select one of the plurality of inputs, (ii) an operational input signal at a selected input during a normal operation of the switch interconnect network, and (iii) an initialization input signal at the selected input during an initialization operation.

Abstract: Techniques and mechanisms for determining an orientation of a connection to an input and/or output (IO) interface of a device. In an embodiment, the device receives one or more signals, each via a respective contact of the IO interface, and identifies the orientation based a signal characteristic of the one or more signals. A communication mode of the device is then configured to accommodate the orientation. A physical arrangement of the IO interface is compatible with a signal plan of an interface type which is defined by an interface specification. The one or more signals are each of a respective signal type other than any signal type which, according to the interface specification, is to provide a basis for orientation identification. In some embodiments, the interface specification is a USB-C specification.

Abstract: Multi-node, multi-socket computer systems and methods provide packet tunneling between processor nodes without going through a node controller link. On receiving a packet, the destination node identifier (NID) is examined, and if it is not same as the source socket, then the packet request address is examined. If it is determined that the packet is not for a remote connected socket, then the packet's destination NID and source socket NID are replaced along with recalculated data protection information. The modified packet is then sent to the destination socket over another processor interconnect path.

Abstract: An electrical power and/or electronic data unit with voice communications capability includes a housing, a voice communications module, and an electrical power outlet coupled to the housing. The voice communications module is coupled to the housing and includes an audio speaker, a microphone, an audio signal receiver/processor, and an audio signal generator. The audio signal receiver/processor is configured to receive and process vocalized speech from a user. The voice communications module is configured to generate an audible response via the audio signal generator and the speaker, responsive to receiving and processing the vocalized speech from the user. The voice communications module is in electronic communication with a data source.

Abstract: A communication channel for reconfiguration of a device, such as an FPGA, is described in various embodiments. One embodiment includes a physical input/output circuit, a dynamic layer, and a static layer. The static layer is programmed into the reconfigurable device to contain a configuration layer and a network layer. The configuration layer is able to receive additional layers, such as a virtual network layer and a virtual security layer and program them into the reconfigurable device. The virtual network layer can provide communication protocols, such as TCP/IP, and the virtual security layer can provide security protocols, such as TLS and IPSec. Various distributed applications can be programmed into the reconfigurable device over the network and configured to use the virtual network layer and the virtual security layer.