Abstract: Multi-node, multi-socket computer systems and methods provide packet tunneling between processor nodes without going through a node controller link. On receiving a packet, the destination node identifier (NID) is examined, and if it is not same as the source socket, then the packet request address is examined. If it is determined that the packet is not for a remote connected socket, then the packet's destination NID and source socket NID are replaced along with recalculated data protection information. The modified packet is then sent to the destination socket over another processor interconnect path.

Abstract: An electrical power and/or electronic data unit with voice communications capability includes a housing, a voice communications module, and an electrical power outlet coupled to the housing. The voice communications module is coupled to the housing and includes an audio speaker, a microphone, an audio signal receiver/processor, and an audio signal generator. The audio signal receiver/processor is configured to receive and process vocalized speech from a user. The voice communications module is configured to generate an audible response via the audio signal generator and the speaker, responsive to receiving and processing the vocalized speech from the user. The voice communications module is in electronic communication with a data source.

Abstract: A communication channel for reconfiguration of a device, such as an FPGA, is described in various embodiments. One embodiment includes a physical input/output circuit, a dynamic layer, and a static layer. The static layer is programmed into the reconfigurable device to contain a configuration layer and a network layer. The configuration layer is able to receive additional layers, such as a virtual network layer and a virtual security layer and program them into the reconfigurable device. The virtual network layer can provide communication protocols, such as TCP/IP, and the virtual security layer can provide security protocols, such as TLS and IPSec. Various distributed applications can be programmed into the reconfigurable device over the network and configured to use the virtual network layer and the virtual security layer.

Abstract: System, methods, and apparatuses for indicating the configured port width for ganged-style data connectors. An exemplary apparatus comprises a plurality of connectors supporting data connections and a plurality of visual indicators. The plurality of connectors are capable of being configured with two or more of the plurality of connectors ganged together to provide increased data width connections. Each or the visual indicators is associated with one of the plurality of connectors. An electrical circuit drives the plurality of visual indicators and is configured to control the visual indicators to visually indicate a configured port width for each data connection supported by the connectors, including those formed by ganging together two or more of the connectors.

Abstract: Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.

Abstract: In one embodiment, a data message is generated at a first system-on-chip (SOC) for transmission to a second SOC. A stream of data words is generated from the data message, the data words alternating between even and odd data words. Each data word in the stream of data words is divided into a first pattern of slices for even data words and a second pattern of slices for odd data words, with the slices distributed across plural output ports at the first SOC. At each output port, two slices from two successive cycles are grouped. The grouped slices are encoded using an encoding scheme to produce an N-bit symbol at M-bits per cycle, alternating between high and low parts of the encoding. Plural metaframes are generated from a stream of symbols and the metaframes for each of the output ports are transmitted to the second SOC.

Abstract: The present disclosure provides a system and method for enabling a flexible PCIe topology in a computing system. The flexible PCIe topology can allow a user to adjust PCIe connections between CPUs and components of the computing system based upon a specific application. In some implementations, the computing system comprises a plurality of CPUs, a plurality of GPUs or Field-Programmable Gate Arrays (FPGAs), a plurality of PCIe switches, and a plurality of network interface controllers (NICs). In some implementations, the computing system comprises a switch circuit to connect the plurality of CPUs, the plurality of PCIe switches, and the plurality of NICs. The switch circuit comprises a plurality of inputs and a plurality of outputs to connect the plurality of CPUs, the plurality of PCIe switches and the plurality of NICs. Connection routes within the switch circuit can be adjusted to set a specific PCIe topology of the computing system.

Abstract: An authentication and information system for use in a surgical stapling system includes a microprocessor configured to demultiplex data from a plurality of components in the surgical system. The authentication and information system can include one wire chips and a coupling assembly with a communication connection.

Abstract: An instrumentation chassis includes a backplane, multiple peripheral slots located on the backplane and configured to receive insertable peripheral modules, respectively, and at least one protocol agnostic high speed connection mounted on, but not electrically connected to the backplane. The high speed connection is configured to interconnect at least two peripheral modules in corresponding peripheral slots of the multiple peripheral slots, bypassing the backplane.

Abstract: A device has a host port, a remote terminal (RT), an incoming line driver, an outgoing line driver, and at least one of an incoming message filter and an outgoing message filter. The host port communicatively couples to a shared host bus. The RT port communicatively couples to the RT. The incoming message filter receives an incoming host message from the host port and generates a filtered host message from the incoming host message employing at least one host message rule. The outgoing message filter receives an outgoing RT message from the RT port and generates a filtered RT message from the outgoing RT message employing at least one RT message rule. The incoming line driver communicates the filtered host message to the RT port. The outgoing line driver communicates the filtered RT message to the host port.

Abstract: A universal serial bus type-C interface circuit and a pin bypass method thereof are provided. The interface circuit includes a first configuration channel pin, a second configuration channel pin, a port manager and a port controller. The port manager has a first signal terminal and a second signal terminal. The port controller includes a multiplexer circuit and a control logic circuit. The multiplexer circuit is coupled to the first configuration channel pin, the second configuration channel pin, the first signal terminal and the second signal terminal. The control logic circuit is coupled to the multiplexer circuit and provides a multiplexer control signal to the multiplexer circuit in response to a switching request. The multiplexer circuit couples the first configuration channel pin and the second configuration channel pin to the first signal terminal and the second signal terminal respectively according to the multiplexer control signal.

Abstract: An electronic control unit connected to a communication line, the electronic control unit including: a transmission request buffer including a plurality of transmission buffer areas; a message buffer including a plurality of message buffer areas; a transmission controller configured to transmit data stored in the message buffer to the communication line; and a central processing unit. The central processing unit programmed to search for data with a higher priority than data stored in the message buffer from among pieces of data stored in the transmission request buffer, sequentially search for a vacant buffer area in which no data is stored from among the plurality of message buffer areas, set the data that has been searched for in the vacant buffer area that has been searched for.

Abstract: Systems, methods, and apparatus are described. An apparatus provides a clock signal, transmits an address on a second line of the serial bus followed by a read/write bit configured to initiate a read transaction, and delays a pulse in the clock signal after transmitting the read/write bit. The pulse may be delayed for a first duration configured to accommodate a latency associated with a first slave device that is a participant in the read transaction. The apparatus may receive an acknowledgement from the first slave device while the pulse is being transmitted and may receive a first data byte from the first slave device after receiving the acknowledgment. The apparatus may stall the clock signal for a second duration after receiving the first data byte from the first slave device, and receive a second data byte from the first slave device after the acknowledgment.

Abstract: A printed circuit board having reduced routing congestion and a method of connecting components on a printed circuit board is disclosed. In one embodiment, a printed circuit board includes a memory controller and memory device. Signal pins of the memory controller and the first memory device are organized into one or more buses based on common functionality, which may be address, data, or command, or any combination thereof. The printed circuit board further includes a plurality of traces connecting each of the signal pins of the memory controller to any one the signal pins of the first memory device belonging to the same bus. The memory controller is configured to associate each one of the signal pins of the memory controller with one of the signal pins of the first memory device that are connected by a plurality of traces.

Abstract: An industrial safety controller comprises a non-volatile memory configured for storing an industrial control program and at least one processing unit. The industrial safety controller, which may be a safety relay, further comprises a connector configured to communicatively couple the safety controller with an expansion module. The safety controller is configured to receive an input and/or provide an output via an I/O expansion module that is coupled to the safety controller utilizing the connector. The industrial safety controller may comprise an expansion module bay and the connector may comprise a bay connector.

Abstract: A first write transaction is received by a device that includes a transaction identifier and a memory location identifier. The memory location identifies a register or a memory location of a device. A value from the register or memory location is read. A second write transaction is sent to a block of host memory. The second write transaction includes the value and the transaction identifier.

Abstract: Described is an I3C Repeater. The I3C Repeater may have a first circuitry with an I3C interface, a second circuitry with an I2C interface, and a datapath circuitry coupled to the first circuitry and the second circuitry. The second circuitry may be operable to convert a transaction received on the I2C interface into a transaction for the I3C interface, and to convert a transaction received on the I3C interface into a transaction for the I2C interface. The I3C Repeater may also have additional circuitries operable to convert transactions received on one of an SPI interface, a UART interface, and a Debug bus interface into transactions for the I3C interface, and vice-versa.

Abstract: A portable patient-care kit is disclosed. The kit includes two-housing portions, a plurality of compartments, a touch-screen user interface device, and a light bar. The two-housing portions pivotally coupled together to form a container space. The plurality of compartments is disposed within at least one of the housing portions such that each compartment is configured to retain at least one medical apparatus. The touch-screen user interface device has a transceiver that can communicate via a mobile data network. The light bar is disposed along an exterior of one of the two-housing portions configured provide light.

Abstract: The present disclosure discloses a communication method for a slave device connected to a master device via an I2C bus. The method includes detecting the condition of a byte end flag when the slave device is in a transmission mode, and clearing the byte end flag to stop transmitting data to the master device as the slave device is in the transmission mode when the byte end flag is detected to be in a first condition. The first condition indicates all data requested by the master device has been transmitted by the slave device. The present disclosure further discloses a slave device using the above-mentioned communication method. When the slave device is in the transmission mode, it is unnecessary to switch the operation mode of the slave device to stop the slave device from continuing transmitting data when the last byte of data has been transmitted.

Abstract: Improvements over existing data collection interfaces disclosed herein include, among other things, additional logic blocks (and associated timers, state machines, and registers) to off-load data collection and data processing prior to waking a microprocessor from a sleep mode. For example, an improved data collection interface collects a predetermined number of sensor values from a sensor while maintaining active a single communication session with the sensor over a pin of the interface. The microprocessor remains in the sleep mode for an entire duration of the single communication session. The data collection interface can reduce the likelihood of false starts of the microprocessor by using the logic blocks to verify that data meet preconditions prior to interrupting the microprocessor. The data collection interface can reduce the overall power consumption of a chip in which the microprocessor is integrated by a factor of at least about 2× (i.e., 50% reduction in power consumption).