Abstract: The present invention provides method and associated interface circuit for mitigating interference due to signaling of a bus between two electronic apparatuses. The method may include: via the bus mechanically compliant to a bus specification, communicating and transporting data at a nonstandard speed which is not compliant to the bus specification. The method may further include: before communicating and transporting data at the nonstandard speed, signaling via the bus at a standard speed to configure a speed switching from the standard speed to the nonstandard speed, with the standard speed compliant to the bus specification. For example, the bus specification may be USB specification, the standard speed may be 5 Gbps (SuperSpeed of USB 3.0 specification), and the nonstandard speed may be lower than the standard speed, e.g., 2.5 Gbps, which forms a spectrum notch at a frequency of wireless connection, e.g., 2.4 GHz of Wi-Fi.

Abstract: A technique for determining if a CPU stalling an RCU grace period has interrupts enabled. Per-CPU state information is maintained for the CPU, including an RCU grace-period number snapshot and an interrupt work-request indicator. If a current RCU grace period has endured for a predetermined time period, it is determined if there is a pending interrupt work request for the CPU. If not, an interrupt work request is generated and the interrupt work-request indicator is updated accordingly. In response to an RCU CPU stall-warning condition, it is determined if the interrupt work request was handled. An RCU CPU stall-warning message reports an interrupt-handling status of the CPU according to the interrupt work request handling determination. If the interrupt work request was not handled, the RCU CPU stall-warning message reports how many RCU grace periods elapsed while the interrupt work request was pending.

Abstract: The embodiments herein provide a secure platform and application virtualization system comprising a universal secure platform virtualization system (USPVS) platform device, a cloud environment and a USPVS portable key device. The USPVS platform is an external computing device having a specific set of protocols to interact with a computing device. The USPVS platform is connected to a plurality of virtual as well as physical cloud environment. The USPVS portable key device is connected to the USPVS platform. The USPVS portable key device holds an encryption key with a Unique ID. The USPVS portable key device comprises a Universal Serial Bus port for connection of a tertiary external device. The USPVS platform has a decryption key for the encryption key of the USPVS portable device.

Abstract: A controller circuit includes a first signal processing device processing signals in accordance with a first predetermined rule, a second signal processing device processing signals in accordance with a second predetermined rule, a data bus coupled between the first signal processing device and the second signal processing device and comprising multiple data lines, and a confirm signal line coupled between the first signal processing device and the second signal processing device. The first signal processing device transmits a synchronization signal to the second signal processing device via the data bus. The second signal processing device estimates transmission delay on each data line according to the synchronization signal, performs transmission delay compensation on each data line according to the estimated transmission delay and transmits a confirmation signal on the confirm signal line to notify the first signal processing device that the transmission delay compensation is complete.

Abstract: Methods and systems that provide for a control path to enable at least one of the two data paths for a network device (e.g., a modem) are provided. An example method includes allowing a device to communicate data, over a network, using a shared control path, within the device, corresponding to a first bus protocol. The method may include using the shared control path, obtaining control information corresponding to a data path, within the device, for allowing the device to communicate data over the network using a network interface. The method may further include automatically determining data transfer capabilities for transmitting or receiving data using the network interface based on the control information, if the data transfer capabilities are determined to be capable of supporting a first data path. The first data path that uses a different protocol from the first bus protocol may be automatically established.

Abstract: Systems and methods for managing name assignments in a Fiber Channel (FC) storage arrays are provided. One example method includes receiving a port name for a slot of a controller of the FC storage array. The slot of the controller is configured to receive an FC card for providing communication between the FC storage array and an FC fabric. The method includes binding the port name to the slot of the controller, and the port name is saved to a database managed by the controller. The method further includes assigning the port name to the FC card when installed in the slot. The FC card is swappable with other FC cards, and thus other FC card will also maintain the port name of the slot.

Abstract: Disclosed are a synchronization processing unit etc. including a command determination unit that determines whether the memory access command is a command for synchronization processing; a completion determination unit that determines whether a memory access command is complete; an issuance unit configured to issue a memory access command determined not to be for the synchronization processing to the memory, and that suspends issuance of a memory access command determined to be for the synchronization processing until completion of a preceding memory access command received before the memory access command for the synchronization processing is determined and then issues the suspended memory access command; and a subsequent control unit that, during a period from the suspension of the memory access command to the issuance and then completion thereof, performs control so that a subsequent memory access command is not received from the external device and the processor in the device.

Abstract: The disclosure discloses a method, device and system for voice interaction, the method including: determining that an external device adopts Universal Serial Bus (USB) 2.0 standard for transmission and the external device supports a voice function; and conducting voice interaction with the external device by adopting customized MIC lines and SPK lines in a micro USB3.0-B female connector interface.

Abstract: A printed circuit board having reduced routing congestion and a method of connecting components on a printed circuit board is disclosed. In one embodiment, a printed circuit board includes a memory controller and memory device. Signal pins of the memory controller and the first memory device are organized into one or more buses based on common functionality, which may be address, data, or command, or any combination thereof. The printed circuit board further includes a plurality of traces connecting each of the signal pins of the memory controller to any one the signal pins of the first memory device belonging to the same bus. The memory controller is configured to associate each one of the signal pins of the memory controller with one of the signal pins of the first memory device that are connected by a plurality of traces.

Abstract: Example embodiments of the present disclosure include an integration system comprising a machine-readable medium (e.g., a memory) and a reconfigurable logic device (e.g., an FPGA). The machine-readable medium stores configuration data that configures the reconfigurable logic device to include a first channel adapter, a first message processor, a second message processor, a message channel, and a second channel adapter. The first channel adapter is configured to receive input data written by a first message endpoint. The first message processor is configured to perform a first message processing operation on messages received from the first channel adapter that include the input data. The second message processor is configured to perform a second message processing operation on messages received from the first message processor. The message channel facilitates communication between the first and second message processors.

Abstract: There is provided an information-sharing device including, in a second device connected to a first device, an information obtaining unit which obtains, through a communication unit of the second device, first application information indicating an application possessed by the first device, a shared information generating unit which generates shared information shared by the first device and the second device, based on the first application information obtained by the information obtaining unit, and a transmission control unit which transmits the shared information through the communication unit to the first device.

Abstract: A method for inspecting a host computer using a USB device, wherein the USB device is selectively operable in a mass storage mode and in a computing mode. The method comprises booting an inspection operating system on the host computer from the USB device, when the USB device is operated in the mass storage mode, the inspection operating system providing one or more inspection functions for inspecting the host computer, switching the USB device from the mass storage mode to the computing mode, and inspecting the host computer using the one or more inspection functions of the inspection operating system, the one or more inspection functions being controlled from the USB device operated in the computing mode.

Abstract: A multilayer butterfly network is shown that is operable to transform and align a plurality of fields from an input to an output data stream. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits. This invention used precalculated inputs and simple combinatorial logic to generate control signals for the butterfly network. Controls are independent for each layer and therefore are dependent only on the input and output patterns. Controls for the layers can be calculated in parallel.

Abstract: A first set of devices is coupled to a first bus, a second bus, and configured to communicate over the first bus according to a first communication protocol. A second set of devices is also coupled to the first bus and configured to communicate over the first bus according to both the first communication protocol and a second communication protocol. In a first mode, the first set of devices and second set of devices may concurrently communicate over the first bus using the first communication protocol. In a second mode, the second set of devices communicate using the second communication protocol over the bus, and the first set of devices to stop operating on the first bus. An enable command is sent by at least one of the second set of devices over a second bus to cause the first set of devices to resume activity over the first bus.

Abstract: A storage apparatus includes a printed circuit board (PCB) and multiple memory chips symmetrically arranged on two sides of the PCB, where multiple memory chips on one side of the PCB form a rank, and multiple memory chips on the other side of the PCB form a rank; a memory chip includes multiple pins; multiple cables are disposed in the PCB; and one cable of the multiple cables is connected to two pins in a same position on the two sides of the PCB.

Abstract: A first write transaction is received by a device that includes a transaction identifier and a memory location identifier. The memory location identifies a register or a memory location of a device. A value from the register or memory location is read. A second write transaction is sent to a block of host memory. The second write transaction includes the value and the transaction identifier.

Abstract: A system including: a master device configured to generate a first signal having a periodic pulse, wherein the first signal includes data; and a slave device including a pin, a delay circuit, a buffer, and a processing circuit, wherein the slave device receives the first signal at the pin, delays the first signal with the delay circuit to generate a second signal having a first delay, delays the first signal with the buffer to generate a third signal having a second delay, and reads the data from the second signal using the third signal at the processing circuit.

Abstract: An electronic device coupling system includes a plurality of electronic devices. The plurality of electronic devices includes a master device and a plurality of slave devices coupleable to the master device one by one. Each electronic device includes a plurality of bus-bars and a plurality of switch modules. Each switch module includes a plurality of switch paths each corresponding to one of the plurality of bus-bars. Two of the electronic devices are inserted together by two of the plurality of bus-bars located in the two of the electronic devices respectively. When the two of the electronic devices are inserted together, the switch paths of each switch module corresponding to the two of the plurality of bus-bars are switched on.

Abstract: A method and apparatus of performing a data transmission from an electronic device or a peripheral device of an electronic device to a peripheral device of a remote electronic device is disclosed. One example method of performing the data transmission may include transmitting data designated for the remote peripheral device to a local virtual device object. The data that is received by the local virtual device object is transmitted via at least one communication interface or peripheral device of the electronic device to at least one remote communication interface or peripheral device of the remote electronic device. The data arriving at the least one remote communication interface or peripheral device of the remote electronic device is received by a remote virtual device object and transmitted to the designated remote peripheral device.

Abstract: A memory system includes a first plurality of nonvolatile memory devices of a first channel of the memory system, the first plurality of memory devices each being connected to a first communications bus; a second plurality of nonvolatile memory devices of a second channel of the memory system, the second plurality of memory devices each being connected to a second communications bus, and a first interconnection between a first memory device and a second memory device, the first memory device being a memory device from among the first plurality of nonvolatile memory devices, the second memory device being a memory device from among the second plurality of nonvolatile memory devices.