Abstract: A data processing method and apparatus, the method comprising: storing, at a first memory location in a memory, a first copy of a set of data; storing, at a second memory location in a memory, a second copy of a set of data; comparing the first copy to the second copy so as to identify, within the first copy, a pointer, the pointer being located at a first data element of the first copy, the pointer specifying a second data element of the first copy; determining an offset for the identified pointer, the offset specifying a number of data elements between the first data element and the second data element; and modifying the first copy such that the pointer within the first copy specifies the second data element using only the first data element and the offset.

Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.

Abstract: Embodiments of the present disclosure relate to a method, a device, and a computer program product for managing data transfer. A method for managing data transfer is provided, including: if determining that a request to transfer a data block between a memory and a persistent memory of a data storage system is received, obtaining a utilization rate of a central processing unit of the data storage system; and determining, from a first transfer technology and a second transfer technology and at least based on the utilization rate of the central processing unit, a target transfer technology for transferring a data block between the memory and the persistent memory, the first transfer technology transferring data through direct access to the memory, and the second transfer technology transferring data through the central processing unit. Therefore, the embodiments of the present disclosure can improve the data transfer performance of the storage system.

Abstract: An ALUA/aggregated switch latency reduction system includes a switch aggregation system coupling a server system including initiator devices to a storage system including target devices. The switch aggregation system includes a respective first switch device directly coupled to each of the target devices, and a respective second switch device directly coupled to each of the initiator devices. Each second switch device identifies an initiator device it is directly connected to, and transmits a respective first communication to each of the first switch devices that identifies that directly connected initiator device. When each second switch device receives a respective second communication from each of the first switch devices that identifies its directly connected target device, it identifies the first switch device directly connected to the target device that is in a session with its directly connected initiator device and, in response, causes packets to be forwarded to that first switch device.

Abstract: An information processing device includes: a memory; and a processor coupled to the memory and configured to: store first execution information that includes first processing for a plurality of data and second processing executed subsequently to the first processing; convert the first execution information into second execution information by making a start timing of the second processing earlier than an end timing of the first processing, under a restriction of an execution order in which a data read in the second processing is executed after a data write in the first processing for each of the plurality of data, on the basis of an order of data writes included in the first processing and an order of data reads included in the second processing; and output the second execution information.

Abstract: A method for optimizing performance of a storage system includes creating a structured state index from a universe of I/O traces of memory access operations in a storage system. The structured state index is validated against a target metric operational parameter of the storage system. If the structured state index has correlation against the target metric operational parameter of the storage system, the structured state index is used as input to a decision-making task. The decision-making task may be implemented as a deep neural network and the structured state index is used as input training data for the deep neural network. Once the decision-making task has been trained using the structured state index, the decision-making task is used in a predictive manner to generate a predicted target metric operational parameter of the storage system given a proposed storage policy.

Abstract: A sensor unit includes at least one sensor for detecting and converting measured quantities into sensor signals; at least one microprocessor; at least one memory for program modules for processing sensor signals, the program modules being executable on the microprocessor; and at least one communications interface to an external application processor, the program modules being able to be activated and deactivated via this communications interface, and further program modules are able to be loaded into the memory via this communications interface. The microprocessor includes at least one closed environment for executing plug-in program modules.

Abstract: An apparatus and method are provided for handling ordered transactions. The apparatus has a plurality of completer elements to process transactions, a requester element to issue a sequence of ordered transactions, and an interconnect providing, for each completer element, a communication channel between that completer element and the requester element for transfer of signals between that completer element and the requester element in either direction. A given completer element that is processing a given transaction in the sequence is arranged to issue a response signal to the requester element over its associated communication channel that comprises an ordered channel indication to identify whether the associated communication channel has an ordered channel property. The ordered channel property guarantees that processing of transactions issued by the requester element over the associated communication channel in a given order will be completed by the given completer element in the same given order.

Abstract: Example implementations relate to SATA and NVMe device determination. An example method can include determining a device type communicatively coupled to an M.2 socket of a central processing unit (CPU) based on a PEDET signal from the M.2 socket. The method can include configuring a crossbar switch to route a plurality of serial AT attachment (SATA) signals to the M.2 socket in response to a determination that the device is a SATA device type. The method can include configuring the crossbar switch and a multiplexer to route a plurality of non-volatile memory express (NVMe) signals to the M.2 socket in response to a determination that the device is an NVMe device type.

Abstract: A multilayer butterfly network is shown that is operable to transform and align a plurality of fields from an input to an output data stream. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits. This invention used precalculated inputs and simple combinatorial logic to generate control signals for the butterfly network. Controls are independent for each layer and therefore are dependent only on the input and output patterns. Controls for the layers can be calculated in parallel.

Abstract: A method, an improvement evaluation system and a computer readable medium are usable for automatically calculating an improvement evaluation result for operating a set of registered applications. Each of the set of registered applications of the system includes a declaration interface, adapted for providing a self-declaration by way of a formula, indicating whether the application is operated under pre-defined success conditions; and a collector, adapted for collecting measurement data during runtime to be introduced in the formula. The system further includes a network for transferring the formula to an evaluation unit for evaluation; and a result interface for providing an improvement evaluation result, reflecting an improvement potential for the respective application to be operated in the set of applications.

Abstract: Methods and systems for data retention in zone storage are disclosed. A method includes: ingesting, by a computing device, a plurality of data objects into a dispersed storage network (DSN); writing, by the computing device, the plurality of data objects to at least one zone on a storage medium in the DSN; determining, by the computing device, that a compaction threshold corresponding to the at least one zone on the storage medium in the DSN is met; determining, by the computing device, that a retention window corresponding to the at least one zone on the storage medium in the DSN has expired; and in response to determining that the retention window has expired, the computing device compacting the at least one zone on the storage medium in the DSN.

Abstract: Example object storage systems, bookkeeping engines, and methods provide quota-based access control for control entities, such as accounts, users, and buckets. An object data store is configured to enable control entities to access data objects associated with each control entity. Quota thresholds and usage values are determined for control entities and used to determine a quota status. Quota status is used to determine data object access response based on the requesting control entities.

Abstract: The application discloses a data processing device, a data processing method and a digital signal processing device. The data processing device is used to reduce computing amount by reading and writing operation of memory. The data processing device comprises: a module for calculating reduced coefficient matrices, a storage module, a module for modifying reduced coefficient matrices, a module for triangular inversing, a module for obtaining inversion matrices and a module for correcting reverse result.

Abstract: According to one embodiment, an electronic apparatus includes a connection unit configured to be capable of being connected to a host device, a storage unit configured to store device classes of a plurality of types, a processing unit configured to execute processing for establishing communication with the host device connected to the connection unit by selectively using one device class from among the device classes stored in the storage unit, and a processing control unit configured to change the device class to be used for the processing by the processing unit if a message appropriate for the selected device class is not transmitted from the host device.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, are described for performing asymmetric data communication at a host-device interface of a system. The methods include identifying devices coupled to a host of the system and generating a system topology that identifies a connectivity of the devices and identifies bus lanes that enable data transfers at the system. The host determines that a first connection between the host and a first device of the multiple devices has an asymmetric bandwidth requirement. The host configures a set of bus lanes of a data bus connecting the first device and the host to allocate a different number of the bus lanes to data egress from the host than to data ingress to the host. The bus lanes are configured to allocate the differing number of bus lanes based on the asymmetric bandwidth requirement of the first connection.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and an operation method. The present disclosure may divide user data and map data corresponding to the user data into data segments, may input the data segments in N virtual die queues, and may program the same in a memory device, wherein a user data segment input in the virtual die queue is programmed according to two program schemes, thereby quickly programming the user data and the map data in the memory device and quickly updating the map data in a map cache.

Abstract: Provided are techniques for automatically detecting and configuring a variety of spray system components. The techniques include a controller configured to detect one or more spray system components. The controller is also configured to initialize software drivers corresponding to the spray system components upon connection of the spray system components to the controller. The techniques may provide one or more hardware on top (HAT) boards configured to couple to the controller and the spray system components.

Abstract: A memory system includes a memory device and a controller suitable for controlling the memory device based on read counts for a plurality of pages of the memory device, wherein the controller counts at least one of the read counts in response to a read request, determines whether there is a page whose read count is initialized at every check-pointing period to generate a determination result, and controls the memory device to update the read counts based on the determination result.

Abstract: An authentication and information system for use in a surgical stapling system includes a microprocessor configured to demultiplex data from a plurality of components in the surgical system. The authentication and information system can include one wire chips and a coupling assembly with a communication connection.