Abstract: An evaluation system for computer performance resulting from user generated information at a remote workstation. The system 6 includes interfaces 8, 9 between the computer 5 and the workstation 14 and means 10 for recording user generated information and computer responses and times associated therewith. A processor 11 identifies known commands and responses to produce a user profile taking into account the user thinking time and typing rate or intercharacter times. The playback block 12 allows repeated reproduction of the original user's actions with the original delays including thinking times and intercharacter times associated therewith. During playback, the response times of the computer for commands and character echo times are measured and stored for analysis by block 13. Such analysis allow statistics for different system configurations or load conditions to be provided.

Abstract: A data management method and system of memo information utilizing a data base can store personal memo information at a high storage efficiency and a high retrieval efficiency without adding a retrieval key to the data base. The data management system may be constructed by connecting a work station having a file for storing memo information to an existing data base system. The system has keys for indicating records of the data base and storage addresses of the corresponding memo information as a connective index file, and refers to it to store, retrieve or delete the memo information. A plurality of memo information for the same record may be displayed on a display of the work station in a time sequence and the memo information are paged.

Abstract: A portable computer, which may be a hand held computer useful for field work, has an attachment which can serve as both a carrying handle for the computer and a stand for holding the computer in a convenient position for use on a desk, at an appropriate angle for viewing the screen. The stand and handle has two plate-like arms connected by a hinge which serves as the handle and with one of the arms securable by a snap-in arrangement to the back or underside of the computer. The computer may have an expansion module secured to its backside, in which case the arm of the stand/handle is secured to the back of the expansion module. In one embodiment the stand and handle device is permanently second to the computer, rather than detachable.

Abstract: A patient care facility communication system with a plurality of communication terminals operatively coupled together for the transmission and receipt of messages, includes a program providing a message composition facility by which an operator may select one or more common items from a plurality of data screens, such as patient lists, address lists, work-item lists, and common message lists, to be included in messages frequently required to be sent for the efficient operation of the patient care facility.

Abstract: A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microcomputer has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxiliary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle.

Abstract: One of several processes is performed for the automatic management of footnote references in printed documents and a computer-controlled display shows bibliographically correct information in long form and short form in a processing system that provides for information to be enterd, stored, analyzed, merged, and transmitted to a printing device for the creation of a printed report that contains footnotes, endnotes or embedded notes which reference a source of information in correctly-reported style.

Abstract: A programmable logic unit performs only monadic, dyadic logic bit level, rather than arithmetic, operations in order to achieve high speed. The unit is formed of section for each output bit position. Each section includes a general function block which simultaneously performs as desired, one or more of the operations cntl1.A.B, cntl2.A.B, cntl3.A.B and cntl4.A.B, wherein A, A, B, B and cntl1 to cntl4 are logic signals and control signals respectively. The inputs of the general function block are connected to a data distribution bus via a multiplex circuit. This connection between the multiplex inputs and the distribution bus can be selected as desired (once), so that the number of different logic operations that can be selected is very large.

Abstract: A microcomputer of this invention includes an internal memory. These memories are connected to internal buses and external buses through bi-directional buffers. This microcomputer also includes a buffer controller for determining whether an access by a control section is made to the internal memory or the access is made to an external memory. When the control section accesses the internal memories, the buffer controller controls the directions of the bi-directional buffers to enable data transfer from the external to the internal bus side. When the controller accesses the external memory, bi-directional buffers are controlled to enable data transfer from the internal to the external bus side.

Abstract: In accordance with the present invention, system architecture and programming are in accordance with a bulk-synchronous parallel processing model. Data is distributed to memory elements through a hashing function performed in individual hardware modules associated with computational elements. The router operates independently of the computational and memory elements and masks any substantial latency it may have by pipelining. A synchronizer provides for bulk synchronization in supersteps of multiple computational steps. The router bandwidth is balanced with that of the computational elements and the program may be compiled to a number of virtual processors significantly greater than the number of actual processors in the system.

Abstract: A method and apparatus for processing two high speed signals through a single high speed input terminal of a microprocessor uses a multiplexing circuit connected between the signal conditioners from the wheel speed sensor and the microprocessor. The multiplexing circuit converts the square wave signal as generated by the signal conditioning circuits into a series of interrupts. The multiplexing circuit includes three hardware semaphores or flip-flops which are set by the interrupts generated from wheel speed signals. The semaphores or flip-flops are reset by the microprocessor.

Abstract: A Data Access System for a File Access Processor for servicing requests from a set of Application Support Processors, which can exist in a global network, with each Application Support Processor sharing access to data in files stored by the File Access Processor. The File Access Processor manages access to a set of data files and information about files held in file directories, which allow for managing file collections, can relate to each other hierarchically, and may be shared. Each Application Support Processor also maintains therein an internal cache of file information to improve performance by reducing communications required with the File Access Processor for information about files. The File Access Processor provides the Application Support Processors with information for updating and maintenance of local caches of directory and file description information through a centralized accumulation and distribution of cache change notifications.

Abstract: In a programmed machine, such as an peripheral controller, programmed operations are executed in a one of several operational contexts. Each context may be initiated by a corresponding interruption signal. Any context which has been activated remains active until quiesced by program execution. One of the active contexts is a current context in which all instruction executions are currently occurring. In each cycle of the programmed machine, all active contexts and received and stored interruption signals, each for respective ones of the contexts, are compared to find the context highest priority context. Such highest priority context is compared with the current context priority for determining whether or not the programmed machine should change current contexts.

Abstract: A personal computer such as one of the IBM 5550 range (represented by the IBM 5530, 5540 and 5560) cannot be connected to a label printer because the two machines have completely different control commands. If a converter is placed between a personal computer of the said type and the label printer, the converter can convert or arrange the data, loop-back anh meaningless or unsuitable signals passing between the two devices, and discard any unnecessary control commands, thus permitting personal computers of the above type, which are increasingly popular, to be connected to a label printer and used effectively, and further permitting the online printing of tags and labels via a connection to a host computer.

Abstract: In a multiprocessor machine comprising K channels of different signals, the signals are converted to digital samples by K analog-to-digital converters connected respectively to each channel. N monolithic elementary processors are connected by means of a sample acquisition bus which is common to all of the K analog-to-digital converters. They are also connected by a ring bus which is common to all of the processors so as to permit circulation between processors of the results of computation performed on the samples received by each processor. A control unit and at least one transfer automat synchronized by a common clock signal initiate respectively on the one hand the performance of computations to be carried out by the processors on the samples which they receive as well as on the other hand the transfer of samples on the acquisition bus and the transfer of the results of computation between processors on the ring bus.

Abstract: A single chip high speed VLSI data filter is disclosed. The data filter performs relational and simple numeric operations on a high speed input data stream using a unique instruction set containing no branching instructions.

Abstract: An electronic disk subsystem for use with data processing equipment has an electronic disk control unit and an electronic disk unit and compares, in a write mode operation, the address of the last data with the content of a counter which is built in the disk unit. The subsystem, therefore, reliably detects an error which may occur in the counter.

Abstract: A multi-processor, multi-tasking virtual machine comprises processes, messages, and contexts. Processes communicate only through messages. Processes may be grouped into contexts of related processes. Communication may be made between processes in different or related contexts or at the same context level.According to one message transmission mode, a message may be sent to each process with a given name within one context, thus ensuring that all processes with the same name at the same context level can be communicated with individually without knowing how many there are or where they are located.

Abstract: A microcomputer comprises EEPROM provided as a fixed storage unit and a CPU for controlling the operation of the EEPROM, in which the EEPROM contains a divider which divides a stable clock signal from the outside of the microcomputer and converts it to a clock signal with a desired frequency, the clock signal is used as a synchronizing signal necessary for the writing data into the EEPROM. The CPU controls the operation of the EEPROM and sets the dividing ratio of the divider contained in the EEPROM at a desired value in accordance with the assignment from the outside of the microcomputer.

Abstract: The efficiency of a processor in which a packet is stored in a receiver buffer, processed in a central processing unit, and sent out via a transmitter buffer, is low. According to the invention, data is transferred to a high-speed memory via the receiver memory. When the high-speed memory is filled with data, the data is processed by the CPU, and the packet is transmitted from the high-speed memory via the transmitter memory. A competition control section is provided to control data accesses in the sequential operation.

Abstract: A combining switch 10 includes a two input multiplexer 12 which receives I and J inputs from data processors and directs one of the incoming messages, if there are no contentions of congestions at a switch output port 14 and a Quene FIFO 16 is empty, directly to the output port 14 for transmission to one of a plurality of memory modules. If the output port 14 is busy and the Queue 16 is empty the incoming message is routed to the Queue FIFO 16 for storage. If the Queue FIFO 16 is not empty the incoming message is first compared by a comparator 20 to all existing messages stored in the Queue FIFO 16 to determine if the incoming messasge is destined for a memory address which already has a queued message. If no match is determined by comparator 20 the incoming message is routed to the Queue FIFO 16 for storage.