Patents Examined by Debra A. Chun
  • Patent number: 5210843
    Abstract: The invention provides a pseudo set-associative memory cacheing arrangement for use in a data processing system comprising a processor interfacing to a main memory and adapted to support a cache memory. The arrangement comprises a plurality of cache memory banks each comprising a respective number of addressable locations individually defined by a cache address. A plurality of cache select circuits are each associated with a respective one of the cache memory banks and each one is responsive to m most significant bits of a main memory address and control signals for mapping its associated cache memory bank to a predetermined range of addresses in main memory.
    Type: Grant
    Filed: June 24, 1992
    Date of Patent: May 11, 1993
    Assignee: Northern Telecom Limited
    Inventor: David J. Ayers
  • Patent number: 5210828
    Abstract: A plurality of processors are connected to the interprocessor communications facility in the multiprocessing system of the invention. The interprocessor communications facility has arbitration circuitry, mailbox circuitry, and processor interrupt circuitry. The interprocessor communications facility of the invention is centralized and does not require the use of main storage. This enables processors to communicate with each other in a fast and efficient manner. The arbitration circuitry prevents simultaneous access of the interprocessor communications facility by more than one processor, and decodes the commands sent from the processors and routes them to the processor interrupt circuitry or to the mailbox circuitry, depending on the command. The mailbox circuitry of the invention receives messages from sending processors and provides them to the intended receiving processors in a safe and secure manner.
    Type: Grant
    Filed: April 4, 1990
    Date of Patent: May 11, 1993
    Assignee: International Business Machines Corporation
    Inventors: Timothy V. Bolan, Josephine A. Boston, George A. Fax, Donald J. Hanrahan, Bernhard Laubli, David A. Ring, Alfred T. Rundle, David J. Shippy
  • Patent number: 5206943
    Abstract: A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility interface and the buffer memory. DMA controllers are also provided between the disk interface and the buffer memory. One of these DMA channels includes an XOR engine used to develop parity information used with the disk array. The various DMA controllers are cycled to allow access to the buffer memory and the disk interface.
    Type: Grant
    Filed: November 3, 1989
    Date of Patent: April 27, 1993
    Assignee: Compaq Computer Corporation
    Inventors: Ryan A. Callison, Thomas W. Grieff, Kenneth L. Bush
  • Patent number: 5206950
    Abstract: A system and method for specifying a computer program. The specified computer program comprises a set of selected program objects, represented by a corresponding set of outline items arranged in a multilevel outline format. These outline items collectively and completely denote the nature and operation of the specified computer program. Each outline item has a set of predefined characteristics, including a set of required children, and a set of optional children, comprising outline items that must/may be included at the next lower outline level when this outline item is used in a computer program. For each outline item in a computer program an expansion denoting flag denotes whether the corresponding outline item has children and whether the display of those children has been enabled. A selected contiguous portion of the multilevel outline is shown on the computer system's display device, showing only outline items whose display is enabled by corresponding expansion display denoting flags.
    Type: Grant
    Filed: July 8, 1991
    Date of Patent: April 27, 1993
    Assignee: Gupta Technologies, Inc.
    Inventors: Michael E. Geary, Umang P. Gupta, David W. Roth, Donal B. Scott
  • Patent number: 5206952
    Abstract: A fault tolerant network for a plurality of computers includes a system for controlling access to shared peripherals. Access to the shared peripherals is coordinated among the computers by means of communication through a semaphore box. Each computer connects to the semaphore box via a channel. The semaphore box is comprised of two major sections: a semaphore section and an I/O section. The semaphore section contains two sets of semaphores: a first set comprising reservation semaphores for the shared peripherals; and a second set comprising heartbeat semaphores for the sharing computers. The first set is used to reserve a particular peripheral for a particular computer and indicate the source of the reservation; the second set provides a "heartbeat" to prevent reservation semaphores from being set indefinitely in the event communication with a particular computer is lost.
    Type: Grant
    Filed: September 12, 1990
    Date of Patent: April 27, 1993
    Assignee: Cray Research, Inc.
    Inventors: James W. Sundet, Roger G. Brown
  • Patent number: 5202965
    Abstract: The invention pertains to electronic data processing systems including a plurality of removable units that communicate with one another via a bus. To enable disconnection or connection of the removable units without interrupting the operation of the system, each unit includes first means (4) controlled selectively by a maintenance device, to assure the functional isolation of the removable units. The system further includes second means (8, 1B) capable of causing the reception devices (1) of the units to function by a mode that procures increased immunity to interference for them.
    Type: Grant
    Filed: July 29, 1992
    Date of Patent: April 13, 1993
    Assignee: Bull, S.A.
    Inventors: Claude Ahn, Robert Chikli-Pariente, Rolland Marbot
  • Patent number: 5197005
    Abstract: A database retrieval system having a natural language interface is provided. A database developer creates a knowledge base containing a structural description and semantic description of an application database from which data is to be retrieved. A database independent, canonical internal meaning representation of a natural language query is produced. An expert system accesses structural and semantic description information in the knowledge base and, in accordance with predefined rules, identifies database elements from said information that are necessary to satisfy the query represented by the internal meaning representation. A database query is generated among the database elements, enabling the retrieval and aggregation of data from the database to satisfy the natural language query. A debugging facility derives an external meaning representation from the internal meaning representation.
    Type: Grant
    Filed: May 1, 1989
    Date of Patent: March 23, 1993
    Assignee: Intelligent Business Systems
    Inventors: Steven Shwartz, Claudio Fratarcangeli, Richard E. Cullingford, Gregory S. Aimi, Donald P. Strasburger
  • Patent number: 5193169
    Abstract: An image data processing apparatus has: a reading portion for reading an image of an original and outputting the image data thereon, an encoding portion for encoding the image data which has been output from the reading portion, an image memory for storing the encoded data which has been output from the encoding means, and a DMA control portion for DMA transferring the encoded data which has been output from the encoding portion to the image memory. The DMA control portion successively selects a plurality of DMA channels, and DMA transfers the encoded data using a selected DMA channel.
    Type: Grant
    Filed: April 25, 1989
    Date of Patent: March 9, 1993
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yuji Ishikawa
  • Patent number: 5193150
    Abstract: A data transfer apparatus, in which when significant length data having a data length longer than the capacity of a communication bus is inputted/outputted through the communication bus into/from a data storage means, a part or the whole of the data transferred through the communiction bus is temporarily stored in a transfer processor so as to combine the data to be in the form of the significant length data so that the significant length data formed by the transfer processor supplied to the data storage means.
    Type: Grant
    Filed: September 1, 1989
    Date of Patent: March 9, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Ikuo Takeuchi, Kohji Kamejima, Tomoyuki Hamada, Norihisa Miyake
  • Patent number: 5187782
    Abstract: An instruction is constituted by a plurality of words, minimum necessary information necessary for effective address calculation of an operand is stored in a leading word and a word or words containing an operation specification field (operation words) are arranged to continue the first word. According to this system, the operation word can be decoded concurrently with the address calculation of the operand or the operand fetch operation. Therefore, there is no need to secure a time exclusively for decoding the operation word and the execution speed of the instruction requiring the operand can be improved.
    Type: Grant
    Filed: July 13, 1990
    Date of Patent: February 16, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Ikuya Kawasaki, Keiichi Kurakazu, Hideo Maejima
  • Patent number: 5185878
    Abstract: Methods and apparatus are disclosed for realizing an integrated cache unit (ICU) comprising both a cache memory and a cache controller on a single chip. The novel ICU is capable of being programmed, supports high speed data and instruction processing applications in both Reduced Instruction Set Computers (RISC) and non-RISC architecture environments, and supports high speed processing applications in both single and multiprocessor systems. The preferred ICU has two buses, one for the processor interface and the other for a memory interface. The ICU support single, burst and pipelined processor accesses and is capable of operating at frequencies in excess of 25 megahertz, achieving processor access times of two cycles for the first access in a sequence, and one cycle for burst mode or piplined accesses. It can be used as either an instruction or data cache with flexible internal cache organization.
    Type: Grant
    Filed: December 12, 1990
    Date of Patent: February 9, 1993
    Assignee: Advanced Micro Device, Inc.
    Inventors: Gigy Baror, William M. Johnson
  • Patent number: 5185879
    Abstract: A cache system which, when a cache is a bus master, puts a CPU in a standby state and makes effective a signal common to the CPU and cache and a signal decided only by the cache, or when the CPU is the bus master, makes effective the signal common to the CPU and cache and the signal decided only by the CPU, or when at a cache miss, the cache gives the CPU a control signal requesting reexecution of memory access and a control signal to allow the memory system to accept memory access to thereby operate the cache dependently on the CPU, so that even when either the CPU or the cache is the bus master, signal transmit-receive with respect to the memory system is adapted to be carried out substantially at the same timing.
    Type: Grant
    Filed: July 22, 1991
    Date of Patent: February 9, 1993
    Inventors: Akira Yamada, Tatsuo Yamada
  • Patent number: 5179658
    Abstract: An information processing apparatus having a scanner and a magnetic disk, both for supplying data to be stored, and an optical disk for storing the supplied data. The scanner supplies image data. The magnetic disk supplies code data such as document data and drawing data. The processing apparatus stores the image data and the code data into the optical disk, each type of data having a flag indicating its type.
    Type: Grant
    Filed: October 24, 1991
    Date of Patent: January 12, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Izawa, Shiro Takagi, Tadanobu Kamiyama
  • Patent number: 5179530
    Abstract: Multiple special purpose processing units are provided in a vector signal processor for concurrent, parallel processing, particularly of complex vectors. The principal processing units are an execution unit, a data movement unit, a control/register unit, a vector buffer unit, an instruction fetch unit, and a bus interface unit.
    Type: Grant
    Filed: May 31, 1991
    Date of Patent: January 12, 1993
    Assignee: Zoran Corporation
    Inventors: Alexander Genusov, Ram B. Friedlander, Peter Feldman, Vlad Fruchter, Ricardo Jaliff, Asaf Mohr, Rafi Retter
  • Patent number: 5179668
    Abstract: The invention relates to a signal processor to be built into a controller or the like for receiving various input signals and generating control signals according to the input signals. The signal processor includes an internal bus interconnecting various components of the signal processor. The invention also includes a first input-output controller for controlling the application of input signals to the signal processor and the output of control signals from the signal processor. The first input-output controller operates under the control of a switch in which the switching criteria for the switch is whether or not the signal processor is using its internal bus. Accordingly, the first input-output controller is allowed access to the signal processor depending on whether or not the internal bus of the signal processor is being used.
    Type: Grant
    Filed: June 5, 1991
    Date of Patent: January 12, 1993
    Assignee: Omron Corporation
    Inventors: Hideji Ejima, Hajime Nishidai
  • Patent number: 5175841
    Abstract: A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microcomputer has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxilary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle.
    Type: Grant
    Filed: January 2, 1990
    Date of Patent: December 29, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: Surendar S. Magar, James F. Potts, Jerald G. Leach, L. Ray Simar, Jr.
  • Patent number: 5165025
    Abstract: By interlacing the two program paths after the test part of a conditional branch, both program paths are available (with minimal delay) from a simple instruction fetch mechanism. Further, the interlacing of program paths continues only until one path ends with an unconditional branch or return.
    Type: Grant
    Filed: May 30, 1991
    Date of Patent: November 17, 1992
    Inventor: Stanley E. Lass
  • Patent number: 5163153
    Abstract: A method and apparatus for configuring a computer in a low-power mode are provided. In the low-power mode, dynamic random access memory is refreshed by a battery powered system in order to maintain the memory contents. Low-power mode is entered by saving an interrupt mask and by disabling interrupts, followed by saving the DMA status, finishing DMA operations, and disabling DMA. After these steps, the I/O state of the machine is saved by saving various I/O registers and ports. A refresh of the memory is forced before the system refresh operations are discontinued.
    Type: Grant
    Filed: June 5, 1991
    Date of Patent: November 10, 1992
    Assignee: Grid Systems Corporation
    Inventors: James F. Cole, James H. McNamara
  • Patent number: 5163141
    Abstract: A memory system for use in a text entry system is provided. The system includes a retentive data memory and a system for locking a portion of the retentive memory and a key for unlocking the lockable portion of the memory to allow a predetermined number of bits of data to be written to the memory when the lockable memory is in unlocked state. The system automatically locks the memory after the predetermined number of bits have been written into the lockable portion of memory.
    Type: Grant
    Filed: August 1, 1988
    Date of Patent: November 10, 1992
    Assignee: Stenograph Corporation
    Inventors: David J. Mueller, Denis B. Flynn, Keith A. McCready, Paul G. Dussault
  • Patent number: 5159672
    Abstract: Circuitry which when combined with an EPROM in a single integrated circuit for connection to a microprocessor which provides suitable signals utilized by the additional circuitry to provude faster access to the code or data stored in the EPROM than can be accomplished without such additional circuitry by providing zero wait state burst performance. A state machine is utilized to manage the interface between the microprocessor and the burst EPROM.
    Type: Grant
    Filed: December 28, 1989
    Date of Patent: October 27, 1992
    Assignee: Intel Corporation
    Inventors: Joseph H. Salmon, Robert E. Larsen, David A. Leak, Kurt B. Robinson, Dhiraj Parmar