Patents Examined by Denise Tran
  • Patent number: 11029848
    Abstract: A file management method, a distributed storage system, and a management node are disclosed. In the distributed storage system, after receiving a file creation request sent by a host for requesting to create a file in a distributed storage system, a management node allocates, to the file, first virtual space from global virtual address space of the distributed storage system, where local virtual address space of each storage node in the distributed storage system is corresponding to a part of the global virtual address space. Then, the management node records metadata of the file, where the metadata of the file includes information about the first virtual space, and the information about the first virtual space is used to point to local virtual address space of a storage node that is used to store the file. Further, the management node sends, the information about the first virtual space to the host.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: June 8, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jun Xu, Junfeng Zhao, Yuangang Wang
  • Patent number: 11003373
    Abstract: A method for managing physical-to-logical address information in a memory system includes determining whether a memory fragment of a memory block is a last memory fragment of the memory block. The method also includes, in response to a determination that the memory fragment is not the last memory fragment of the memory block: performing a write operation on the memory fragment; storing, in cache associated with the memory system, physical-to-logical address information associated with the memory fragment; and, in response to a determination that the cache is full, writing, to a next memory fragment of the memory block, control metadata associated with physical-to-logical address information stored in the cache.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 11, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Niraj Srimal, Ramanathan Muthiah
  • Patent number: 10983918
    Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Carminantonio Manganelli, Yoav Weinberg, Alberto Sassara, Paolo Papa, Luigi Esposito, Giuseppe D'Eliseo, Angelo Della Monica, Massimo Iaculo
  • Patent number: 10970104
    Abstract: A resource access method applied to a computer and the computer, where the resource access method is performed by a resource controller which is used to implement resource virtualization. The method includes receiving a resource access request of a virtual machine (VM) for a resource, where the resource access request carries a resource virtual address and an identifier of the VM, translating the resource virtual address into a resource physical address using the identifier of the VM and based on a preset resource information mapping relationship, updating the resource virtual address in the resource access request using the resource physical address, and sending an updated resource access request to a to-be-accessed resource corresponding to the resource physical address in order to access the to-be-accessed resource.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: April 6, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Zihao Yu, Jiuyue Ma, Yungang Bao
  • Patent number: 10942860
    Abstract: A computing system using a bit counter may include a host device; a cache configured to temporarily store data of the host device, and including a plurality of sets; a cache controller configured to receive a multi-bit cache address from the host device, perform computation on the cache address using a plurality of bit counters, and determine a hash function of the cache; a semiconductor device; and a memory controller configured to receive the cache address from the cache controller, and map the cache address to a semiconductor device address.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: March 9, 2021
    Assignees: SK hynix Inc., Korea University Industry Cooperation Foundation
    Inventors: Seonwook Kim, Wonjun Lee, Yoonah Paik, Jaeyung Jun
  • Patent number: 10942859
    Abstract: A computing system using a bit counter may include a host device; a cache configured to temporarily store data of the host device, and including a plurality of sets; a cache controller configured to receive a multi-bit cache address from the host device, perform computation on the cache address using a plurality of bit counters, and determine a hash function of the cache; a semiconductor device; and a memory controller configured to receive the cache address from the cache controller, and map the cache address to a semiconductor device address.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: March 9, 2021
    Assignees: SK hynix Inc., Korea University Industry Cooperation Foundation
    Inventors: Seonwook Kim, Wonjun Lee, Yoonah Paik, Jaeyung Jun
  • Patent number: 10908848
    Abstract: A new snapshot of a storage volume is created by instructing computing nodes to suppress write requests. Once pending write requests from the computing nodes are completed, storage nodes create a new snapshot for the storage volume by allocating a new segment to the new snapshot and finalizes and performs garbage collection with respect to segments allocated to the previous snapshot. An orchestration layer implements a bundled application that is provisioned with virtualized storage and computation resources. A snapshot of the bundled application may be created and used to rollback or clone the application. Clones snapshots of storage volumes may be gradually populated with data from prior snapshots to reduce loading on a primary snapshot. Chaos testing of the bundled application may be performed and storage volumes may be created, expanded, and/or moved based on usage of the bundled application.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: February 2, 2021
    Assignee: ROBIN SYSTEMS, INC.
    Inventors: Ashok Mishra, Ravikumar Alluboyina
  • Patent number: 10896125
    Abstract: Methods and systems are provided for performing a garbage collection scheme for hybrid address mapping. A controller of a memory system receives data and a logical address for the data from a host device, writes the data in a page of an open log block and performs a garbage collection on a log block and under a certain condition, one or more data blocks, when the open log block is full.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: January 19, 2021
    Assignee: SK hynix Inc.
    Inventors: Aman Bhatia, Naveen Kumar, Yu Cai, Fan Zhang
  • Patent number: 10891240
    Abstract: Systems, methods, and apparatuses relating to low latency communications in a configurable spatial accelerator are described.
    Type: Grant
    Filed: June 30, 2018
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Suresh Mathew, Mitchell Diamond, Kermin E. Fleming, Jr.
  • Patent number: 10884621
    Abstract: Block volume mount synchronization is provided. A call is received to mount a block volume upon initiation of container generation on the host computer. Metadata of the block volume is checked for host lock prior to mounting the block volume on the host computer. The mounting of the block volume is allowed only when the metadata indicates that prior host lock does not exist thereby restricting usage of the block volume to a single user preventing data corruption of the block volume.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Akash V. Gunjal, Shaikh I. Ali, Sushma Korati
  • Patent number: 10853269
    Abstract: A secure demand paging system including a secure internal memory, an external non-volatile memory having encrypted and integrity-protected code pages, an external volatile memory for swap pages and a processor coupled to said secure internal memory and to said external non-volatile memory and operable to decrypt and verify the integrity of the code pages thereby to transfer code pages to said secure internal memory directly from said external non-volatile memory bypassing said external volatile memory in respect of the code pages, and to swap out and swap in the swap pages between secure internal memory and said external volatile memory bypassing said external non-volatile memory in respect of the swap pages for said external volatile memory.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: December 1, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Steven C. Goss, Gregory Remy Philippe Conti, Narendar M. Shankar, Mehdi-Laurent Akkar, Aymeric Vial
  • Patent number: 10852967
    Abstract: Apparatuses and methods are described that provide for a mechanism for allocating physical device memory for one or more virtual functions. In particular, a memory allocating framework is provided to utilize device memory more efficiently by mapping at least one target location of the physical memory in a Base Address Register (BAR) associated with the virtual function from a plurality of available target locations based on an allocation request. The memory allocating framework is further configured to compare an indication associated with the requesting virtual function to an identifier of the requested target location. Moreover, the memory allocating framework is further configured to allow the simultaneous use of more than one virtual function at a time while providing isolation between multiple virtual functions.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: December 1, 2020
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Ariel Shahar, Peter Paneah, Maxim Zaborov
  • Patent number: 10838645
    Abstract: Generally, a computing system includes processing circuitry, such as one or more processors or other suitable components, and memory devices, such as chips or integrated circuits. The memory devices may be associated with thermal limits. Saving data in such a way that causes a thermal limit of the memory device to be exceeded may cause loss of stored data and/or device over-heating. As discussed herein, a memory controller associated with the processing circuitry may determine whether a thermal limit is expected to be exceeded for a current memory writing operation. When the thermal limit is expected to be exceeded, the memory controller may respond by modifying the memory operation in such a manner that the thermal limit is not exceeded, thereby improving operation of at least the memory device and/or memory controller.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Reshmi Basu, William Leins Stube, II, Anthony Joseph Dupont, Michael Richard Ives
  • Patent number: 10839885
    Abstract: Steering logic circuitry includes bit-flipping logic that determines a first neighboring redundant word line adjacent to a redundant word line of a memory bank, which also includes normal word lines. Redundant word lines include main word lines, each of which includes paired word lines. Each paired word line includes two redundant word lines. The steering logic circuitry also includes border determination logic that determines whether the redundant word line is on a border between the redundant word lines and an end of the memory bank or the normal word lines. The steering logic circuitry further includes main word line steering logic that determines a neighboring main word line that a second neighboring redundant word line adjacent to the redundant word line is disposed in, and paired word line steering logic that determines a neighboring paired word line that the second neighboring redundant word line is disposed in.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Joosang Lee
  • Patent number: 10809921
    Abstract: Systems, methods, and computer readable storage mediums for discovering volumes which are good candidates for space reclamation. A storage subsystem identifies the file system storage capacity for a given volume from the file system metadata of the given volume. Then, the storage subsystem compares the file system capacity of the given volume to the allocated capacity on the storage subsystem. If the allocated capacity is greater than the file system capacity by a given threshold, the storage subsystem marks the given volume as a candidate for space reclamation and generates an alert to the user to reclaim the space of the given volume.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: October 20, 2020
    Assignee: Pure Storage, Inc.
    Inventors: Frederic Lherault, Neil Vachharajani
  • Patent number: 10782892
    Abstract: Systems, methods, and computer readable storage mediums for discovering volumes which are good candidates for space reclamation. A storage subsystem identifies the file system storage capacity for a given volume from the file system metadata of the given volume. Then, the storage subsystem compares the file system capacity of the given volume to the allocated capacity on the storage subsystem. If the allocated capacity is greater than the file system capacity by a given threshold, the storage subsystem marks the given volume as a candidate for space reclamation and generates an alert to the user to reclaim the space of the given volume.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: September 22, 2020
    Assignee: Pure Storage, Inc.
    Inventors: Frederic Lherault, Neil Vachharajani
  • Patent number: 10782910
    Abstract: The invention introduces a method for internal data movements of a flash memory device, performed by a host, at least including the following steps: generating an internal movement command when detecting that a usage-status for an I/O channel of a solid state disk (SSD) has met a condition; and providing the internal movement command to direct the SSD to perform an internal data-movement operation in the designated I/O channel.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: September 22, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Sheng-Liu Lin
  • Patent number: 10768816
    Abstract: A method is disclosed for changing data within a solid state drive without using a host interface, comprising issuing a write buffer command with a code to the solid state drive, receiving the code at the solid state drive, storing the code at the solid state drive, transmitting a command to run the code at the solid state drive, running the code with a processor in a virtual machine arranged within the solid state drive, wherein the running of the code alters data within the solid state drive and altering at least one memory arrangement in the solid state drive such that the memory arrangement records the altered data.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: September 8, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Mackenzie Roeser, Robert Hill
  • Patent number: 10768815
    Abstract: Performing a non-disruptive upgrade of data in a storage system that includes a plurality of storage devices and a storage controller, including: creating new data in a new data format, wherein the new data includes a reference to old data in an old data format, wherein system software in the storage system can utilize data in the new data format and the old data format; determining that a portion of the volume has changed; and responsive to determining that the portion of the volume has changed, updating the new data to include a reference to old data associated with a portion of the volume that precedes the changed portion of the volume, new data associated with the changed portion of the volume, and a reference to old data associated with a portion of the volume that follows the changed portion of the volume.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: September 8, 2020
    Assignee: Pure Storage, Inc.
    Inventors: Jianting Cao, Wentian Cui, Christopher Golden, David Grunwald, Scott Smith, Qi Zhou
  • Patent number: 10754565
    Abstract: Systems and methods for providing deferred lock enforcement for transactions are described. The method includes receiving a first request for access to a data resource for a transaction, assigning a first lock to the transaction, and receiving, from a candidate reader, a second request for access to the data resource. The method further includes determining an interpretation of the first lock as i) a first lock type responsive to determining that the transaction is in a read phase or ii) a second lock type responsive to determining that the transaction is in a commit processing phase, and assigning a second lock to the candidate reader responsive to interpreting the first lock as the first lock type, or declining to assign the second lock to the candidate reader responsive to interpreting the first lock as the second lock type.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: August 25, 2020
    Assignee: Google LLC
    Inventor: Goetz Graefe