Patents Examined by Denise Tran
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Patent number: 10908848Abstract: A new snapshot of a storage volume is created by instructing computing nodes to suppress write requests. Once pending write requests from the computing nodes are completed, storage nodes create a new snapshot for the storage volume by allocating a new segment to the new snapshot and finalizes and performs garbage collection with respect to segments allocated to the previous snapshot. An orchestration layer implements a bundled application that is provisioned with virtualized storage and computation resources. A snapshot of the bundled application may be created and used to rollback or clone the application. Clones snapshots of storage volumes may be gradually populated with data from prior snapshots to reduce loading on a primary snapshot. Chaos testing of the bundled application may be performed and storage volumes may be created, expanded, and/or moved based on usage of the bundled application.Type: GrantFiled: October 22, 2018Date of Patent: February 2, 2021Assignee: ROBIN SYSTEMS, INC.Inventors: Ashok Mishra, Ravikumar Alluboyina
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Patent number: 10896125Abstract: Methods and systems are provided for performing a garbage collection scheme for hybrid address mapping. A controller of a memory system receives data and a logical address for the data from a host device, writes the data in a page of an open log block and performs a garbage collection on a log block and under a certain condition, one or more data blocks, when the open log block is full.Type: GrantFiled: November 16, 2018Date of Patent: January 19, 2021Assignee: SK hynix Inc.Inventors: Aman Bhatia, Naveen Kumar, Yu Cai, Fan Zhang
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Patent number: 10891240Abstract: Systems, methods, and apparatuses relating to low latency communications in a configurable spatial accelerator are described.Type: GrantFiled: June 30, 2018Date of Patent: January 12, 2021Assignee: Intel CorporationInventors: Suresh Mathew, Mitchell Diamond, Kermin E. Fleming, Jr.
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Patent number: 10884621Abstract: Block volume mount synchronization is provided. A call is received to mount a block volume upon initiation of container generation on the host computer. Metadata of the block volume is checked for host lock prior to mounting the block volume on the host computer. The mounting of the block volume is allowed only when the metadata indicates that prior host lock does not exist thereby restricting usage of the block volume to a single user preventing data corruption of the block volume.Type: GrantFiled: January 2, 2019Date of Patent: January 5, 2021Assignee: International Business Machines CorporationInventors: Akash V. Gunjal, Shaikh I. Ali, Sushma Korati
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Patent number: 10853269Abstract: A secure demand paging system including a secure internal memory, an external non-volatile memory having encrypted and integrity-protected code pages, an external volatile memory for swap pages and a processor coupled to said secure internal memory and to said external non-volatile memory and operable to decrypt and verify the integrity of the code pages thereby to transfer code pages to said secure internal memory directly from said external non-volatile memory bypassing said external volatile memory in respect of the code pages, and to swap out and swap in the swap pages between secure internal memory and said external volatile memory bypassing said external non-volatile memory in respect of the swap pages for said external volatile memory.Type: GrantFiled: April 13, 2016Date of Patent: December 1, 2020Assignee: Texas Instruments IncorporatedInventors: Steven C. Goss, Gregory Remy Philippe Conti, Narendar M. Shankar, Mehdi-Laurent Akkar, Aymeric Vial
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Patent number: 10852967Abstract: Apparatuses and methods are described that provide for a mechanism for allocating physical device memory for one or more virtual functions. In particular, a memory allocating framework is provided to utilize device memory more efficiently by mapping at least one target location of the physical memory in a Base Address Register (BAR) associated with the virtual function from a plurality of available target locations based on an allocation request. The memory allocating framework is further configured to compare an indication associated with the requesting virtual function to an identifier of the requested target location. Moreover, the memory allocating framework is further configured to allow the simultaneous use of more than one virtual function at a time while providing isolation between multiple virtual functions.Type: GrantFiled: April 26, 2018Date of Patent: December 1, 2020Assignee: Mellanox Technologies, Ltd.Inventors: Ariel Shahar, Peter Paneah, Maxim Zaborov
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Patent number: 10838645Abstract: Generally, a computing system includes processing circuitry, such as one or more processors or other suitable components, and memory devices, such as chips or integrated circuits. The memory devices may be associated with thermal limits. Saving data in such a way that causes a thermal limit of the memory device to be exceeded may cause loss of stored data and/or device over-heating. As discussed herein, a memory controller associated with the processing circuitry may determine whether a thermal limit is expected to be exceeded for a current memory writing operation. When the thermal limit is expected to be exceeded, the memory controller may respond by modifying the memory operation in such a manner that the thermal limit is not exceeded, thereby improving operation of at least the memory device and/or memory controller.Type: GrantFiled: April 22, 2019Date of Patent: November 17, 2020Assignee: Micron Technology, Inc.Inventors: Reshmi Basu, William Leins Stube, II, Anthony Joseph Dupont, Michael Richard Ives
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Patent number: 10839885Abstract: Steering logic circuitry includes bit-flipping logic that determines a first neighboring redundant word line adjacent to a redundant word line of a memory bank, which also includes normal word lines. Redundant word lines include main word lines, each of which includes paired word lines. Each paired word line includes two redundant word lines. The steering logic circuitry also includes border determination logic that determines whether the redundant word line is on a border between the redundant word lines and an end of the memory bank or the normal word lines. The steering logic circuitry further includes main word line steering logic that determines a neighboring main word line that a second neighboring redundant word line adjacent to the redundant word line is disposed in, and paired word line steering logic that determines a neighboring paired word line that the second neighboring redundant word line is disposed in.Type: GrantFiled: July 11, 2019Date of Patent: November 17, 2020Assignee: Micron Technology, Inc.Inventor: Joosang Lee
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Patent number: 10809921Abstract: Systems, methods, and computer readable storage mediums for discovering volumes which are good candidates for space reclamation. A storage subsystem identifies the file system storage capacity for a given volume from the file system metadata of the given volume. Then, the storage subsystem compares the file system capacity of the given volume to the allocated capacity on the storage subsystem. If the allocated capacity is greater than the file system capacity by a given threshold, the storage subsystem marks the given volume as a candidate for space reclamation and generates an alert to the user to reclaim the space of the given volume.Type: GrantFiled: July 13, 2018Date of Patent: October 20, 2020Assignee: Pure Storage, Inc.Inventors: Frederic Lherault, Neil Vachharajani
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Patent number: 10782892Abstract: Systems, methods, and computer readable storage mediums for discovering volumes which are good candidates for space reclamation. A storage subsystem identifies the file system storage capacity for a given volume from the file system metadata of the given volume. Then, the storage subsystem compares the file system capacity of the given volume to the allocated capacity on the storage subsystem. If the allocated capacity is greater than the file system capacity by a given threshold, the storage subsystem marks the given volume as a candidate for space reclamation and generates an alert to the user to reclaim the space of the given volume.Type: GrantFiled: January 31, 2017Date of Patent: September 22, 2020Assignee: Pure Storage, Inc.Inventors: Frederic Lherault, Neil Vachharajani
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Patent number: 10782910Abstract: The invention introduces a method for internal data movements of a flash memory device, performed by a host, at least including the following steps: generating an internal movement command when detecting that a usage-status for an I/O channel of a solid state disk (SSD) has met a condition; and providing the internal movement command to direct the SSD to perform an internal data-movement operation in the designated I/O channel.Type: GrantFiled: June 22, 2018Date of Patent: September 22, 2020Assignee: SILICON MOTION, INC.Inventor: Sheng-Liu Lin
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Patent number: 10768815Abstract: Performing a non-disruptive upgrade of data in a storage system that includes a plurality of storage devices and a storage controller, including: creating new data in a new data format, wherein the new data includes a reference to old data in an old data format, wherein system software in the storage system can utilize data in the new data format and the old data format; determining that a portion of the volume has changed; and responsive to determining that the portion of the volume has changed, updating the new data to include a reference to old data associated with a portion of the volume that precedes the changed portion of the volume, new data associated with the changed portion of the volume, and a reference to old data associated with a portion of the volume that follows the changed portion of the volume.Type: GrantFiled: April 27, 2018Date of Patent: September 8, 2020Assignee: Pure Storage, Inc.Inventors: Jianting Cao, Wentian Cui, Christopher Golden, David Grunwald, Scott Smith, Qi Zhou
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Patent number: 10768816Abstract: A method is disclosed for changing data within a solid state drive without using a host interface, comprising issuing a write buffer command with a code to the solid state drive, receiving the code at the solid state drive, storing the code at the solid state drive, transmitting a command to run the code at the solid state drive, running the code with a processor in a virtual machine arranged within the solid state drive, wherein the running of the code alters data within the solid state drive and altering at least one memory arrangement in the solid state drive such that the memory arrangement records the altered data.Type: GrantFiled: April 23, 2018Date of Patent: September 8, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Mackenzie Roeser, Robert Hill
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Patent number: 10754565Abstract: Systems and methods for providing deferred lock enforcement for transactions are described. The method includes receiving a first request for access to a data resource for a transaction, assigning a first lock to the transaction, and receiving, from a candidate reader, a second request for access to the data resource. The method further includes determining an interpretation of the first lock as i) a first lock type responsive to determining that the transaction is in a read phase or ii) a second lock type responsive to determining that the transaction is in a commit processing phase, and assigning a second lock to the candidate reader responsive to interpreting the first lock as the first lock type, or declining to assign the second lock to the candidate reader responsive to interpreting the first lock as the second lock type.Type: GrantFiled: April 23, 2018Date of Patent: August 25, 2020Assignee: Google LLCInventor: Goetz Graefe
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Patent number: 10740041Abstract: A processing system includes a processing unit and a hardware block configured to change operation as a function of life cycle data. A one-time programmable memory includes original life cycle data. A hardware configuration module is configured to read the original life cycle data from the one-time programmable memory and provide the original life cycle data to the hardware block. The hardware configuration module includes a register providing the life cycle data used to change operation of the hardware block. The hardware configuration module is configured to store the original life cycle data in the register and receive a command from the processing unit. The command includes a write request for storing new life cycle data in the register.Type: GrantFiled: May 29, 2018Date of Patent: August 11, 2020Assignee: STMicroelectronics Application GmbHInventor: Roberto Colombo
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Patent number: 10725925Abstract: A method writing data received from a host device includes determining whether command data of a write command includes metadata, flushing the command data out of a volatile write cache according to a first caching policy responsive to a determination that the command data does includes metadata, and flushing the command data out of the volatile write cache according to a second different caching policy responsive to a determination that the command data does not include metadata.Type: GrantFiled: September 13, 2018Date of Patent: July 28, 2020Assignee: SEAGATE TECHNOLOGY LLCInventors: Chee Hou Peng, Mun Kai Lye, WenXiang Xie, Vincent Uy
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Patent number: 10713162Abstract: A method and a system for accelerating computer data garbage collection (GC) on a non-volatile memory (NVM) computer storage device may include: monitoring, by a processor, a data validity parameter of at least one physical write unit (PWU), where the PWU may include a plurality of physical data pages of the NVM device; sending at least one GC command from the processor to an accelerator associated with the NVM device, based on the monitored data validity parameter; copying, by the accelerator, a plurality of data-objects stored on at least one first PWU, to a read address space comprised within the accelerator; copying valid data-objects from the read address space to a write address space comprised within the accelerator until the amount of data in the write address space exceeds a predefined threshold; and storing, by the accelerator, the data content in at least one second PWU in the NVM media.Type: GrantFiled: April 26, 2018Date of Patent: July 14, 2020Assignee: Lightbits Labs Ltd.Inventors: Shmuel Ben-Yehuda, Ofir Efrati, Roy Geron, Abel Alkon Gordon, Sagi Grimberg, Eran Kirzner, Ziv Tishel, Maor Vanmak, Ofer Hayut
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Patent number: 10691369Abstract: In some examples, with respect to pool partner based replication, a first pool may be generated for a first storage array and may include a first volume of data stored in a storage space of the first storage array. A second pool may be generated for a second storage array and may include a second volume to receive data replicated from the first volume. Based on the generation of the second pool, first and second pool partners respectively representing end points for communication with the first and second pools may be generated. A volume collection may be generated and may include identifications of the first pool partner and the second pool partner, and a first volume identification of the first volume. Based on the volume collection, replication of the first volume may be performed from the first pool to the second volume of the second pool.Type: GrantFiled: April 23, 2018Date of Patent: June 23, 2020Assignee: Hewlett Packard Enterprise Development LPInventors: Naveen Bali, Neha Siddha, Michael E. Root
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Patent number: 10671536Abstract: A method and apparatus for pre-fetching data into a cache using a hardware element that includes registers for receiving a reference for an initial pre-fetch and a stride-indicator. The initial pre-fetch reference allows for direct pre-fetch of a first portion of memory. A stride-indicator is also received and is used along with the initial pre-fetch reference in order to generate a new pre-fetch reference. The new pre-fetch reference is used to fetch a second portion of memory.Type: GrantFiled: October 2, 2017Date of Patent: June 2, 2020Inventors: Ananth Jasty, Indraneil Gokhale
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Patent number: 10664441Abstract: An information processing apparatus, including: a memory unit; and a processor configured to perform a migration process of migrating a migration source file system to a migration target file system, the memory unit is configured to store first and second information, the first information managing a target object of the first migration process stored in the migration source file system and the target object to be stored in the migration target file system, and the second information managing a progress status of the first migration process for each object, the processor is configured to: select either or both of the migration source and target file systems based on the first and second information when a write request for the target object is received from a host apparatus; and perform a process related to the write request on the file system selected.Type: GrantFiled: June 15, 2017Date of Patent: May 26, 2020Assignee: FUJITSU LIMITEDInventors: Yoshiharu Shitara, Yuji Nomura