Abstract: Probabilistic eviction of partial aggregation results may be implemented for aggregation operations performed using constrained result storage. An aggregation operation request may be received from a client and executed by scanning and applying the aggregation operation to data retrieved by scanning a data store. Partial aggregation results that are generated while executing the aggregation operation may be stored in a result store. If a partial aggregation result is generated when no further storage space in the result store is available, then one or more currently stored partial aggregation results may be evicted according to a reoccurrence probability so that the new partial aggregation result may be stored in the result store. The evicted partial aggregation results may be sent to the client.

Abstract: A management system receives a job definition condition that defines a migration job corresponding to partial migration that is part of data migration for replacement from a replace source storage system to a replace target storage system. The management system selects one or more source volumes and creates a migration job for the one or more source volumes in accordance with the job definition condition. The migration job is a job in which, for each of the one or more source volumes, a target volume is created in the replace target storage system, and in which data is migrated from each of the one or more source volumes to a corresponding one of the one or more target volumes. The management system executes each of a plurality of migration jobs.

Abstract: A management server acquires storage and application information from a first system to store the information. The storage information includes storage area correspondence information indicating a correspondence between a storage area and a processor. The application information includes application correspondence information indicating a correspondence between the processor and an application, and application configuration information indicating a past Input/Output (IO) load on the storage area. The management server estimates an IO load on the storage area by the application based on the storage and application information to obtain an estimated value, and determines whether or not a copy processable period, a period in which a copy process of data can be performed is present, based on the data size and the estimated value. When the copy processable period is present, the management server transmits a copy indication including a start time of the copy processable period to a copy processing server.

Abstract: A cache memory system includes cache memories of at least one layer, at least one of the cache memories having a data cache to store data and a tag to store an address of data stored in the data cache, and a first address conversion information storage to store entry information that includes address conversion information for virtual addresses issued by a processor to physical addresses and cache presence information that indicates whether data corresponding to the converted physical address is stored in a specific cache memory of at least one layer among the cache memories.

Abstract: Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.

Abstract: An individual identification device (1) according to embodiments may identify a storage device (100) including one or more memory chips (40). The device comprises a first storage (40), a region allocator (15), and a hardware fingerprint generator (12). The first storage may be configured to store write data. The region allocator may be configured to write the write data in a specific region in each memory chip. The hardware fingerprint generator may be configured to generate hardware fingerprint data based on mismatch bits between the write data and read data read out from the specific region in each memory chip.

Abstract: Performing a non-disruptive upgrade of data in a storage system that includes a plurality of storage devices and a storage controller, including: creating new data in a new data format, wherein the new data includes a reference to old data in an old data format, wherein system software in the storage system can utilize data in the new data format and the old data format; determining that a portion of the volume has changed; and responsive to determining that the portion of the volume has changed, updating the new data to include a reference to old data associated with a portion of the volume that precedes the changed portion of the volume, new data associated with the changed portion of the volume, and a reference to old data associated with a portion of the volume that follows the changed portion of the volume.

Abstract: A data storage device includes a nonvolatile memory device including a buffer region and a main region; and a controller suitable for controlling a buffer write operation of the nonvolatile memory device such that write-requested first data is stored in the buffer region, and controlling a main write operation of the nonvolatile memory device such that the first data stored in the buffer region is stored in the main region according to a write mode, wherein the nonvolatile memory device performs the buffer write operation regardless of the write mode.

Abstract: A hardware data prefetcher is comprised in a memory access agent, wherein the memory access agent is one of a plurality of memory access agents that share a memory. The hardware data prefetcher includes a prefetch trait that is initially either exclusive or shared. The hardware data prefetcher also includes a prefetch module that performs hardware prefetches from a memory block of the shared memory using the prefetch trait. The hardware data prefetcher also includes an update module that performs analysis of accesses to the memory block by the plurality of memory access agents and, based on the analysis, dynamically updates the prefetch trait to either exclusive or shared while the prefetch module performs hardware prefetches from the memory block using the prefetch trait.

Abstract: [Object] Copy processing time is reduced by selecting an optimum copy method according to the content of difference data and the status of a system. [Solution] When the primary disk storage apparatus and the secondary disk storage apparatus are separated from each other after dual writing operation and a copy pair regarding which data is written to only the primary disk storage apparatus is to be resynchronized, the host computer selects either host-computer-based copy processing executed via the host computer or inter-disk-control-device copy processing executed between the first disk control device and the second disk control device, on the basis of information about copy processing including a difference data amount between the primary disk storage apparatus and the secondary disk storage apparatus, a data transfer amount between the respective apparatuses, and performance information of each apparatus.

Abstract: Dynamic random access memory (DRAM) backchannel communication systems and methods are disclosed. In one aspect, a backchannel communication system allows a DRAM to communicate error correction information and refresh alert information to a System on a Chip (SoC), applications processor (AP), or other memory controller.

Abstract: The present disclosure includes methods for operating a memory system, and memory systems. One such method includes updating transaction log information in a transaction log using write look ahead information; and updating a logical address (LA) table using the transaction log. For example, the write look ahead information can include information about a location where data would have next been written a memory system and/or includes information about the location where data had most recently been written a memory system.

Abstract: An apparatus includes a memory storing a group of pages of data. An interface of the apparatus is configured to send, to a data storage device (DSD) from a first command queue, a first instruction of instructions to store the group of pages to the DSD using a logical address corresponding to the group of pages. The interface is further configured to send, to the DSD from a second command queue, a second instruction of the instructions to write the group of pages to the DSD using the logical address. Sending a first copy of the group of pages in association with the first instruction and sending a second copy of the group of pages in association with the second instruction enables a multi-stage programming operation to be performed at the DSD without storing the group of pages at the DSD between stages of the multi-stage programming operation.

Abstract: A cache device connected to a storage device and connected to a plurality of sources, including a cache unit that relays a read request and a read response between a source and a storage device, and a storage area control unit that stores the source as a first history in association with specification of first data in a read request, and, if the first data are not retained by the cache unit and a storage area sufficient for retaining the first data does not exist, selects data associated with a less number of the sources in the first history as second data in preference to data associated with a greater number of the sources out of the first data or data retained by the cache unit, and, if the second data differ from the first data, causes the cache unit to discard the second data and then store the first data.

Abstract: The present invention relates to a computer implemented method and database management system for storing data on a storage device. A plurality of empty files at the storage device is pre-allocated in a processor of the database management system. Each of the empty files has a pre-determined file size. The empty files are overwritten sequentially with a plurality of data blocks. Each of the data blocks having a pre-determined size. The present invention relates to a database management system (DBMS) that coordinates both the physical and the logical components of data management.

Abstract: Techniques are disclosed relating to register caching techniques for thread switches. In one embodiment, an apparatus includes a register file and caching circuitry. In this embodiment, the register file includes a plurality of registers and the caching circuitry is configured to store information that indicates threads that correspond to data stored in respective ones of the plurality of registers. In this embodiment, the apparatus is configured to store, at a point in time at which a first register of the plurality of registers includes first valid data corresponding to a first thread, second valid data corresponding to a second thread in a second register of the plurality of registers. In some embodiments, the disclosed techniques may reduce context switch latency, reduce pressure on a data cache, and/or allow smaller slices of thread execution, for example.

Abstract: A non-volatile memory system and a method of managing the power of the same are provided. The non-volatile memory system includes a non-volatile memory configured to store a first mapping table comprising a list of a logical address and a physical address corresponding to the logical address with respect to a code region and a list of a logical address and a physical address corresponding to the logical address with respect to a general purpose (GP) region, and a controller configured to load the first mapping table from the non-volatile memory to a first memory and load the second mapping table from the non-volatile memory to a second memory. Power-up of the second memory is delayed with respect to power-up of the non-volatile memory system and the first or second memory is powered down if a condition is satisfied, so that power consumption of the non-volatile memory system is reduced.

Abstract: A computing system includes a processor that has a processor cache built-in, and a non-volatile memory, such as a non-volatile dual-inline memory module (NVDIMM), which is being used as system memory within the computing system. The processor processes a transaction. If the computing system is connected to an uninterruptible power supply (UPS) (and the UPS is connected to a mains power source that is currently providing power), the transaction is committed without first flushing the processor cache to the non-volatile memory. If the computing system is not connected to a UPS (and is connected to a mains power source that is currently providing power), the transaction is not committed until the processor cache has been flushed to the non-volatile memory.

Abstract: A method of determining causes of external fragmentation in a memory. The method includes collecting information associated with release of an area of the memory by an application, storing the information in the area of the memory, and analyzing the information to determine why the area of the memory has not been reallocated to any application. In embodiments wherein a first portion of an area of a memory is allocated to an application by an allocator and a second portion of the area of the memory is released by the allocator, the method includes storing in the second portion of the area of the memory an indicator indicating that the second portion is a remaining portion, colleting information associated with release of the second portion, storing the information in the second portion, and analyzing the information to determine why the second portion is not reallocated to any application.

Abstract: A method of determining causes of external fragmentation in a memory. The method includes collecting information associated with release of an area of the memory by an application, storing the information in the area of the memory, and analyzing the information to determine why the area of the memory has not been reallocated to any application. In embodiments wherein a first portion of an area of a memory is allocated to an application by an allocator and a second portion of the area of the memory is released by the allocator, the method includes storing in the second portion of the area of the memory an indicator indicating that the second portion is a remaining portion, colleting information associated with release of the second portion, storing the information in the second portion, and analyzing the information to determine why the second portion is not reallocated to any application.