Abstract: A computer-implemented method includes associating an initial use order with a plurality of target sets of a translation lookaside buffer (TLB), where the initial use order indicates an order of use of the plurality of target sets. The plurality of target sets are associated with an initial least-recently-used (LRU) state based on the initial use order. A new use order for the plurality of target sets is generated. Generating the new use order includes moving a first target set to a least-recently-used position, responsive to a purge of the first target set. The LRU state of the plurality of target sets is updated based on the new use order, responsive to the purge of the first target set. The first target set is identified as eligible for replacement according to an LRU replacement policy of the TLB, based at least in part on the purge of the first target set.

Abstract: The presently disclosed subject matter includes various inventive aspects, which are directed for enabling execution of deduplication during data writes in a distributed storage-system.

Abstract: A method, computer program product, and system for selective memory mirroring including identifying, by a computer during an initial program load, predictively deconfigured memory units and memory interfaces, wherein the predictively deconfigured memory units and memory interfaces are marked by the computer for removal from a computer configuration prior to the initial program load, analyzing the predictively deconfigured memory units and memory interfaces to determine a level of granularity for selective memory mirroring and initiating selective memory mirroring at the determined level of granularity using the analyzed predictively deconfigured memory units and memory interfaces.

Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.

Abstract: In one embodiment, the method includes buffering, under control of a memory controller, received data and an associated program entity in a buffer. The program entity includes first address information and second address information, the first address information indicates an address of the buffer storing the received data, and the second address information indicates an address in the memory to store the received data. The method further includes storing, at the memory controller, management information. The management information includes program information, and the program information includes a pointer to the program entity in the buffer. The method also includes transferring the received data from the buffer to the memory based on the management information and the program entity.

Abstract: An apparatus includes: a cache to retain an instruction; an instruction-control circuit to read out the instruction from the cache; and an instruction-execution circuit to execute the instruction read out from the cache, wherein the cache includes: a pipeline processing circuit including a plurality of selection stages in each of which, among a plurality of requests for causing the cache to operate, a request having a priority level higher than priority levels of other requests is outputted to a next stage and a plurality of processing stages in each of which processing based on a request outputted from a last stage among the plurality of selection stages is sequentially executed; and a cache-control circuit to input a request received from the instruction-control circuit to the selection stage in which processing order of the processing stage is reception order of the request.

Abstract: A computer-implemented method includes associating an initial use order with a plurality of target sets of a translation lookaside buffer (TLB), where the initial use order indicates an order of use of the plurality of target sets. The plurality of target sets are associated with an initial least-recently-used (LRU) state based on the initial use order. A new use order for the plurality of target sets is generated. Generating the new use order includes moving a first target set to a least-recently-used position, responsive to a purge of the first target set. The LRU state of the plurality of target sets is updated based on the new use order, responsive to the purge of the first target set. The first target set is identified as eligible for replacement according to an LRU replacement policy of the TLB, based at least in part on the purge of the first target set.

Abstract: The present disclosure discloses a method and apparatus for inserting a disk. The method comprises: detecting whether a to-be-inserted disk has a drive letter identifier, wherein the drive letter identifier is acquired by a server through: acquiring a universally unique identifier of the disk; querying a correspondence between the universally unique identifier and a device name, acquiring the device name of the disk, analyzing the device name of the disk to generate a drive letter value of the disk, and generating a drive letter identifier for the disk; acquiring the drive letter value in response to detecting the disk identifier; determining whether the device name associated with the drive letter value is allocated to a different disk; and defining the device name of the disk based on the drive letter value so as to insert the disk if the device name is not allocated to the different disk.

Abstract: A cache hierarchy and a method of operating the cache hierarchy are disclosed. The cache hierarchy comprises a first cache level comprising an instruction cache, and predecoding circuitry to perform a predecoding operation on instructions having a first encoding format retrieved from memory to generate predecoded instructions having a second encoding format for storage in the instruction cache. The cache hierarchy further comprises a second cache level comprising a cache and the first cache level instruction cache comprises cache control circuitry to control an eviction procedure for the instruction cache in which a predecoded instruction having the second encoding format which is evicted from the instruction cache is stored at the second cache level in the second encoding format. This enables the latency and power cost of the predecoding operation to be avoided when the predecoded instruction is then retrieved from the second cache level for storage in the first level instruction cache again.

Abstract: A method for screening bad data columns in a data storage medium comprising a plurality of data columns includes: a) labeling or recording a plurality of bad data columns as bad data column group, wherein the bad data columns are selected from the data columns, and each bad data column group labels or records a position and a number of the bad data columns; b) determining whether at least one bad data column is not labeled or recorded; and c) if yes, labeling or recording any two bad data columns spaced apart by P data columns and the P data columns as one of the bad data column groups, wherein P is a positive integer.

Abstract: Dynamic random access memory (DRAM) backchannel communication systems and methods are disclosed. In one aspect, a backchannel communication system allows a DRAM to communicate error correction information and refresh alert information to a System on a Chip (SoC), applications processor (AP), or other memory controller.

Abstract: A storage apparatus includes a storage disk including a plurality of tracks each of which includes a plurality of sectors, a head configured to write data in and read data from the storage disk, and a controller. The controller is configured to control the head to carry out reading of a group of data units from target sectors in a target track of the storage disk, the group of data units being associated with a command received from an external device, determine whether or not the target sectors include one or more defective sectors based on result of the reading, and control the head to write the group of data units in physically consecutive non-written sectors of the target track or another track, when the target sectors are determined to include the defective sectors.

Abstract: A file management method, a distributed storage system, and a management node are disclosed. In the distributed storage system, after receiving a file creation request sent by a host for requesting to create a file in a distributed storage system, a management node allocates, to the file, first virtual space from global virtual address space of the distributed storage system, where local virtual address space of each storage node in the distributed storage system is corresponding to a part of the global virtual address space. Then, the management node records metadata of the file, where the metadata of the file includes information about the first virtual space, and the information about the first virtual space is used to point to local virtual address space of a storage node that is used to store the file. Further, the management node sends, the information about the first virtual space to the host.

Abstract: Embodiments of techniques and systems for execution of code with multiple page tables are described. In embodiments, a heterogenous system utilizing multiple processors may use multiple page tables to selectively execute appropriate ones of different versions of executable code. The system may be configured to support use of function pointers to virtual memory addresses. In embodiments, a virtual memory address may be mapped, such as during a code fetch. In embodiments, when a processor seeks to perform a code fetch using the function pointer, a page table associated with the processor may be used to translate the virtual memory address to a physical memory address where code executable by the processor may be found. Usage of multiple page tables may allow the system to support function pointers while utilizing only one virtual memory address for each function that is pointed to. Other embodiments may be described and claimed.

Abstract: One embodiment provides a method for retrospective snapshot creation including creating, by a processor, a first snapshot that captures logical state of a data store at a first time in a time range. Creation of the first snapshot is based on determining existence of a second snapshot that captures logical state of the data store and recording a retrospective snapshot at a last valid log address offset prior to the first time upon a determination that the second snapshot exists based on determining at least one of: whether log address offsets from a first log entry of a log to a log entry of the log at the first time are contiguous and whether log address offsets from the second snapshot to the first time are contiguous.

Abstract: A secure demand paging system (1020) includes a processor (1030) operable for executing instructions, an internal memory (1034) for a first page in a first virtual machine context, an external memory (1024) for a second page in a second virtual machine context, and a security circuit (1038) coupled to the processor (1030) and to the internal memory (1034) for maintaining the first page secure in the internal memory (1034).

Abstract: A solid state storage device includes a non-volatile memory and a controlling circuit. In a first read retry process, the controlling circuit judges whether an information corresponding to a first block of the non-volatile memory is recorded in the cache table. If the information is not recorded in the cache table, the controlling circuit sequentially provides plural predetermined retry read voltage sets to the non-volatile memory according to a sequence of the plural predetermined retry read voltage sets in the retry table and performs a read retry operation. If a read data of the first block is successfully decoded through the read retry operation according to a first predetermined retry read voltage set of the plural predetermined retry read voltage sets in the retry table, the controlling circuit records the first predetermined retry read voltage set into the cache table.

Abstract: A method, computer program product, and system for selective memory mirroring including identifying, by a computer during an initial program load, predictively deconfigured memory units and memory interfaces, wherein the predictively deconfigured memory units and memory interfaces are marked by the computer for removal from a computer configuration prior to the initial program load, analyzing the predictively deconfigured memory units and memory interfaces to determine a level of granularity for selective memory mirroring and initiating selective memory mirroring at the determined level of granularity using the analyzed predictively deconfigured memory units and memory interfaces.

Abstract: A memory device has a plurality of dedicated data blocks for storing user data and a plurality of dedicated overhead blocks for storing overhead data. A dedicated overhead block of the plurality of dedicated overhead blocks has a plurality of overhead segments. The overhead segments have physical block address registers configured to store physical block addresses defining respective dedicated data blocks.

Abstract: A set associative cache memory comprises an M×N memory array of storage entries arranged as M sets by N ways, both M and N are integers greater than one. Within each group of P mutually exclusive groups of the M sets, the N ways are separately powerable. A controller, for each group of the P groups, monitors a utilization trend of the group and dynamically causes power to be provided to a different number of ways of the N ways of the group during different time instances based on the utilization trend.