Patents Examined by Dennis M. Butler
  • Measuring affective response to content in a manner that conserves power
    Patent number: 9477290
    Abstract: Systems and methods that enable a reduction in the power consumption involved in measuring a user's affective response to content. The reduction in the power consumption is achieved by utilizing tags that indicate a mode of operation in which to operate a sensor when measuring affective response of the user to certain segments of the content. By using at different times, different modes of operation for operating the sensor, which are characterized by different energy consumption rates, the total power consumption of the sensor may be reduced.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: October 25, 2016
    Inventors: Ari M Frank, Gil Thieberger
  • Communication control apparatus, information processing apparatus, and information processing system
    Patent number: 9471135
    Abstract: A communication control apparatus includes: a first receiving unit that receives a power supply packet; a power supply unit that performs a power supply control at the time of detecting reception of the power supply packet; and a second receiving unit that receives a power disconnection packet and outputs the power disconnection packet to an external control apparatus.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: October 18, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Yoshikatsu Wakayoshi
  • Computer device
    Patent number: 9465428
    Abstract: A computer device is disclosed. The computer device includes a central processing unit (CPU), a chipset, an input/output (I/O) chip, a general purpose I/O (GPIO) interface, and a smart battery. The chipset is electrically connected to the CPU. The I/O chip is electrically connected to the chipset. The GPIO interface is electrically connected to the CPU. The smart battery is electrically connected to the GPIO interface and the I/O chip. The CPU reads information of two bytes saved in the smart battery through the GPIO interface and determines a relative processing according to information of two bytes when a status of the smart battery is changed.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: October 11, 2016
    Assignee: QUANTA COMPUTER INC.
    Inventor: Wei-Ting Yen
  • Application defined computing component configuration
    Patent number: 9465622
    Abstract: One embodiment includes a configurable computing system. The configurable computing system includes a broker module that receives information for one or more applications, obtains one or more attributes for an electronic device, and determines runtime configurations for one or more components for the electronic device. A controller communicates with applications for configuring the one or more components based on the runtime configurations.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: October 11, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Arun S. Jagatheesan, Zheng Li, Mahdi Nazm Bojnordi, Jupyung Lee
  • Method and apparatus for acquiring time spent on system shutdown
    Patent number: 9465626
    Abstract: A method for determining time spent on system shutdown is provided. The method may involve identifying a time at which a shutdown instruction is initiated during the system shutdown. Further, an exit time of an object that is the last to exit during the system shutdown may be identified. The time spent on the system shutdown may be determined based on the time at which the shutdown instruction is initiated and the exit time of the object that is the last to exit. The method for determining time spent on system shutdown may obtain the system time spent on the previous system shutdown regardless of the reason that the system was shut down. Further, the user may be instructed to optimize the system according to the time spent on system shutdown.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: October 11, 2016
    Assignee: Tencent Technology (Shenzhen) Company Limited
    Inventor: Xue Wei
  • Modifying disk images
    Patent number: 9459883
    Abstract: A method includes identifying a first boot configuration type for a disk image. The disk image includes a master boot record and a disk partition. The disk partition comprises a volume boot record. The master boot record comprises first instructions for loading an operating system, and the volume boot record comprises second instructions for loading the operating system. The method further includes receiving an input indicative of a second boot configuration type. The method also includes modifying the disk image to use the second boot configuration type to load the operating system by modifying the first instructions and the second instructions.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: October 4, 2016
    Assignee: CA, Inc.
    Inventors: Haiyang Zhang, Xiaopin Wang, Victor Liu, Shaorong Li
  • Irregularity detection device for a power switch
    Patent number: 9448607
    Abstract: An irregularity detection device for a power switch determines if a temperature-dependent resistance on a current path of the power switch is abnormal according to if a voltage on the current path is greater than or equal to a configuration value when the power switch is turned on, and generates an irregularity alarm associated with the power switch based on the determination result.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: September 20, 2016
    Assignee: Acbel Polytech Inc.
    Inventor: Chia-An Yeh
  • Powered device
    Patent number: 9448604
    Abstract: A powered device is electronically connected to power sourcing equipment (PSE), to receive voltage signals from the PSE. The powered device comprises a rectifier unit, a recognition unit, a control unit, a converter and a powered circuit. The recognition unit identifies that the PSE is an Ethernet PSE or a DC PSE. The control unit controls whether the control unit output a negative voltage signal output by the rectifier unit, according to a positive voltage signal output by the rectifier unit and a identified result output by the recognition unit. The converter converts the negative voltage signal and the positive voltage signal to a working voltage of the powered circuit, to drive the powered circuit. To feed power by a single interface and identify that the PSE is the Ethernet PSE or the DC PSE, according to a simple circuit architecture.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: September 20, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Mao-Chang Chuang, Yung-Chiang Cheng
  • System and method for server rack power mapping
    Patent number: 9430010
    Abstract: A server rack includes a rack space having a plurality of rack units for receiving equipment, a power mapping module, and a plurality of power receptacles. Each power receptacle is coupled to the power mapping module to provide an indication to the power mapping module when equipment is plugged in to the power receptacles, uniquely associated with one of the plurality of rack units, and collocated with the associated rack unit. The power mapping module is operable to determine which rack unit of the plurality of rack units that first equipment is installed into, based upon a first power receptacle of the first equipment being coupled to a first power receptacle of the plurality of power receptacles.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: August 30, 2016
    Assignee: Dell Products, LP
    Inventors: John R. Palmer, Syed S. Ahmed, Jinsaku Masuyama
  • Detecting state loss on a device
    Patent number: 9430413
    Abstract: This document describes techniques for detecting state loss on a device. These techniques permit a computer connected to a device to forgo, in many cases, reinitializing the device when returning to a normal-power mode.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: August 30, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Janet L. Schneider, Doron J. Holan, Randall E. Aull
  • System and method for server rack power management
    Patent number: 9423854
    Abstract: A server rack includes a management controller, a power mapping module coupled to the management controller, and a plurality of power receptacles. Each power receptacle is coupled to the power mapping module to provide an indication to the power mapping module of the power consumed by equipment that is plugged in to each power receptacle. The management controller is operable to determine that the power consumed by the equipment installed in the server rack is greater than a first high power threshold and throttle a first piece of equipment installed in the rack space.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: August 23, 2016
    Assignee: Dell Products, LP
    Inventors: John R. Palmer, Syed S. Ahmed, Jinsaku Masuyama
  • Resetting inactivity timer on computing device
    Patent number: 9423856
    Abstract: Computing devices and methods for resetting an inactivity timer of each of a first and second computing device are described. In one embodiment, the method comprises establishing a communication channel between the first computing device and the second computing device, receiving activity input responsive to a user interaction at the first computing device, resetting the inactivity timer of the first computing device, and transmitting a notification via the communication channel to the second computing device that the activity input was received at the first computing device, the inactivity timer of the second computing device being reset in response to receipt of the notification.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: August 23, 2016
    Assignee: BlackBerry Limited
    Inventor: Michael Joseph DeLuca
  • Method for enabling calibration during start-up of a micro controller unit and integrated circuit therefor
    Patent number: 9417884
    Abstract: A method for enabling calibration during start-up of a micro controller unit device is provided. The method comprises, within the MCU device, reading overlay initialization data from at least one memory element within an external support device operably coupled to the MCU device, and configuring memory mapping functionality of the MCU device to overlay data stored within at least a part of device memory of the MCU device with calibration data stored within the at least one memory element of the external support device in accordance with the overlay initialization data.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: August 16, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Mark Maiolani, Alistair Robertson
  • Power management apparatus, image forming apparatus and power management method
    Patent number: 9395807
    Abstract: A sleep mode in which power consumption is reduced to a prescribed value or smaller is achieved, while convenience for a user is maintained by shortening the time taken to recover from the sleep mode. The temperature of an LSI is measured or estimated when shifting to the sleep mode, and an apparatus enters a power supply shutoff sleep mode using power supply separation or a clock-gating sleep mode in accordance with the measured or estimated value of the temperature. In the case where power supply shutoff is selected, after entering the sleep mode, power supply is resumed and then the apparatus enters the clock-gating sleep mode in accordance with the measured temperature or the estimated temperature of the LSI.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: July 19, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Toshio Yoshihara
  • Rectifier circuit and powered device
    Patent number: 9389662
    Abstract: A powered device is electronically connected to a power sourcing equipment, and includes a powered circuit, a receiving unit and at least one rectifier circuit. Each rectifier circuit includes a rectifier unit, an auxiliary power unit, a polarity determining unit, a control unit and a selecting unit. The rectifier unit provides a current flow between the receiving unit and the powered circuit. The auxiliary power unit provides an auxiliary power signal. The polarity determining unit detects the polarity of voltage signal, to generate a determining signal. The control unit outputs a control signal according to the auxiliary power signal and the determining signal. The selecting unit connects the positive input of the powered circuit to a receiving end whose output voltage is positive according to the control signal, to lower power of rectification. A rectifier circuit is also provided.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: July 12, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Yi-Guo Chiu
  • Method and apparatus for implementing a secure boot using multiple firmware sources
    Patent number: 9384351
    Abstract: Technologies for implementing a secure boot using multiple firmware sources are described. One or more fuses of a processing device can be configured. Based on such configuration, one or more keys can be generated. Based on the configuration of the various fuses, an operation of a firmware device can be initiated. Using the generated key(s), a protected section of the firmware device can be accessed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Ivan Herrera Mejia, Kenneth D. Shoemaker
  • Circuit design for balanced logic stress
    Patent number: 9383767
    Abstract: An electronic system is disclosed, which may include a phase pipeline, a data pipeline, an input phase selector, and an output phase selector. The phase pipeline may have latches clocked by a clock signal, and designed to propagate phase signals from a phase input to a phase output. The data pipeline may have latches clocked by the phase pipeline clock signal, and designed to propagate data from a data input to a data output. The input phase selector may be designed to provide an inverted or a non-inverted copy of data from a data input, in response to a value at the phase input, to the data pipeline data input. The output phase selector may be designed to provide an inverted or a non-inverted copy of data from the data pipeline output to an output phase selector data output, in response to a phase pipeline output value.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: July 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Nathaniel R. Chadwick, Frances S. M. Clougherty, William P. Hovis, Kirk D. Peterson, Mack W. Riley
  • Timing control device and control method thereof
    Patent number: 9385691
    Abstract: Provided is a timing control device including: a storage unit that stores multiple pieces of timing control information including identification information and expected value data; a first selector that selectively outputs any of the multiple pieces of timing control information; a second selector that selectively outputs any of data items output from data output devices based on the identification information; a reference data generation unit that generates reference data based on expected value data and a data item output from the second selector in synchronization with a switching of the timing control information; a comparator that compares the reference data with the data item output from the second selector and outputs a coincidence signal when the reference data and the data item coincide with each other; and an output control unit that outputs a timing signal according to the coincidence signal.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: July 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Atsushi Takahashi
  • Data center in a rack
    Patent number: 9377832
    Abstract: A server rack comprises a battery string connected to a controller and rectifier, server slots, a server load located in a first server slot of the server slots, a second server load stored in a second server slot of the server slots, a first AC power supply circuit supplying power to the first server load, a second AC power supply circuit supplying power to the second server load, a first DC power supply circuit supplying power to the first server load, a second DC power supply circuit supplying power to the second server load, a DC power distribution circuit connecting the rectifier to the first DC power supply circuit and the second DC power supply circuit, and an AC power distribution circuit connecting an incoming AC power supply to the first AC power supply circuit and the second AC power supply circuit.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 28, 2016
    Assignee: Twitter, Inc.
    Inventor: Ali Heydari Monfared
  • Semiconductor integrated circuit, information processing apparatus, and control method
    Patent number: 9360921
    Abstract: In a system large-scale integration (LSI) including a plurality of subsystems having a power shutdown mechanism, sometimes instantaneous power consumption of the LSI intensively increases at timing of supplying a clock for initialization due to a shift of a power mode of a subsystem. After power supply starts to return to a first subsystem and a second subsystem, an increase in power consumption during initialization is distributed by desynchronizing timing of clock supply to start initialization for the first subsystem and the second subsystem.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 7, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kazuya Kayama