Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. In one particular case, a system is disclosed that includes a first data processing circuit operable to apply a data detection algorithm to a data input synchronous to a first clock, and a second data processing circuit operable to apply a subsequent data processing algorithm to an output derived from the first data processing circuit synchronous to a second clock, and an idle time enforcement circuit operable to modify an average frequency of at least one of the first clock and the second clock.

Abstract: In accordance with the present disclosure, a system and method for providing scalable and modular power infrastructure outside of usable rack space is described. The system may include a chassis configured to mount on the side of a rack. A power cable interface box (PCIB) may be disposed within the chassis, and the PCIB may receive alternating current (AC) power. The system may further include at least one power supply unit disposed within a slot of the chassis, with the at least one power supply unit receiving AC power from the PCIB and outputting direct current (DC) power to a busbar. The system may also include a battery back-up unit (BBU) element disposed within the chassis. The BBU element may charge from and discharge to the busbar.

Abstract: In a case where a first condition is met while a communication device may in a high consumption state, the communication device may transit to a first low consumption state. In a case where a second condition is met while the communication device is in a specific state which is one state of the high consumption state and the first low consumption state, the communication device may transit to a second low consumption state. The communication device may be configured to execute a packet process in a case where a receiving process for receiving a packet is executed after the communication device had transited to the first low consumption state. The communication device may be configured not to execute the packet process in a case where the receiving process for receiving the packet is executed after the communication device had transited to the second low consumption state.

Abstract: When there is a memory module mounted in a memory slot, a memory power circuit provides a voltage to the memory slot. First and second power pins of the memory slot are connected. A first electronic switch is turned on. A second electronic switch is turned off. A programmable logic controller (PLC) outputs a first control signal to the memory power circuit to output the voltage to the memory slot. When there is no memory module mounted in the memory slot and the motherboard is powered on, the memory power circuit provides a voltage to the memory slot. The first and second power pins of the memory slot are disconnected. The first electronic switch is turned off. The second electronic switch is turned on. The PLC outputs a second control signal to control the memory power circuit not to output the voltage to the memory slot.

Abstract: A method of flashing a BIOS memory of a computer system is described herein. The method includes executing a kernel of baseboard management controller (BMC) to create a partition for the BMC memory and a second partition for the BIOS memory; detecting whether the host processor is accessing the BIOS memory; controlling a multiplexer (MUX) to allow the first processor to access the BIOS memory when the host processor is not accessing the BIOS memory; and retrieving first BIOS software from the BMC memory and writing the first BIOS software to the BIOS memory.

Abstract: A device for descrambling encrypted data includes a descrambler, a secure link, and a secure element that securely transmits a control word to the descrambler in a normal operating mode. The secure element includes a first secure register, a read-only memory having a boot code, a random-access memory for storing a firmware image from an external memory, and a processor coupled to the first secure register, the read-only memory, and the random access memory. The processor executes the boot code to generate the control word, stores the control word in the first secure register, and send the stored control word to the descrambler through a secure communication link. The descrambler may include a second secure register that is connected to the first secure register through the secure link. The first and second secure registers are not scannable during a normal operation. The secure link contains buried signal traces.

Abstract: A circuit includes a central processing unit (CPU), which includes a first memory block having a first power domain; and a core block signally connected to the first memory block and having a second power domain disconnected from the first power domain.

Abstract: An electronic device sets run types and startup information for applications within the electronic device, where each run type is associated with a signal triggered by a hardware component of the electronic device and the startup information of each application comprises a run type and a starting time of the application. In response to detecting a signal triggered by a hardware component of the electronic device, and having an application having a run type associated with the signal, the electronic device further determines if a time of triggering the signal accords with a starting time of the application. The application is started if the time of triggering the signal accords with the starting time of the application.

Abstract: An apparatus includes a storage unit configured to store information which is acquired by a negotiation with an external apparatus and is for communication via a network, a detection unit configured to detect that conditions are satisfied for switching to a power saving mode in which power consumption is smaller than in a normal power mode while the normal power mode is operating, and a notification unit configured to notify a network interface of the stored information when the conditions for switching to the power saving mode are satisfied.

Abstract: A data storage device is disclosed comprising a non-volatile memory having a host operating system stored in an unprotected area of the non-volatile memory, a device operating system stored in a protected area of the non-volatile memory, and a device application operable to modify a web browser file, the device application stored in the protected area of the non-volatile memory. When a first read command is received from a host to load the host operating system, the device operating system is returned in response to the first read command. A second read command is then received from the host to load the device application, and a write command is received from the device application executing on the host to modify the web browser file.

Abstract: A latency control circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a clock signal by a delay time varied according to any one of dual locking points, and generate a loop change signal according to a locking point change; a control unit configured to generate a latency control signal in response to a reset signal, a delay signal generated by delaying the reset signal by a first delay time, and the loop change signal; and a latency signal generation unit configured to adjust a latency of a command signal in response to the latency control signal and output a latency signal.

Abstract: This disclosure describes systems, methods, and apparatus for reducing power consumption of an application processor in a user equipment. State information of applications that indicate an expected load requirement that the applications will likely place on the application processor, can be used to control power management features of the application processor. For instance, an operating frequency of the application processor, or online cores of the application processor, can be reduced. The number of online cores (those that are not idled) can also be changed to tailor performance and power consumption to the load requirement. Other power management techniques such as adjusting core operational voltage can also be implemented.

Abstract: Various methods for performing energy management via a sub-system are provided. One example method includes receiving a user input while a main processing system is in a power saving mode and buffering a representation of the user input. The example method further includes, in response to receiving the user input, triggering a wake up of a main processing system from the power saving mode, and causing transmission of the representation of the user input to the main processing system for processing. Similar and related example methods and example apparatuses are also provided.

Abstract: A method for securely generating and distributing encryption keys includes generating, by a secured server, a pair of keys including a first key and a second key and providing, by a key distributing unit, the first key to a first recipient and a second key to a second recipient. The first recipient may use the first key to encrypt a data file and send the encrypted data file via a non-volatile memory device to a target subscriber. The second recipient may program the second key into an one-time-programmable register contained in a secure element during a manufacturing process. The secure element may further include a random access memory configured to store an image of the encrypted data file, a read-only memory containing a boot code, and a processing unit coupled to the random-access memory and the read-only memory and operative to decrypt the encrypted data file.

Abstract: A method for controlling a multitasking microprocessor system includes monitoring the multitasking microprocessor system connected to an interconnect, the monitoring comprising monitoring performance of a plurality of processing units forming a producer-consumer system on the interconnect, and issuing commands to the plurality of processing units to provide operations and power distributions to the plurality of processing units such that the performance and power modes are assigned to the plurality of processing units based on the monitoring.

Abstract: Systems and methods for transforming an initial quantum state to a target quantum state are disclosed. The initial quantum state is denoted by superposed initial quantum sample states and the target quantum state is denoted by superposed target quantum sample states. The initial quantum state is initialized with a set of primary registers for the initial quantum state and with at least one ancillary register. The initial quantum state is transformed such that the set of primary registers reflects the initial quantum sample states and the at least one ancillary register is varied to compose an intermediate quantum state. In addition, the intermediate quantum state is amplified by implementing quantum state rotations in accordance with a plurality of reflections on the intermediate quantum state such that the reflections result in the target quantum sample states of the target quantum state with a discarding of the at least one ancillary register.

Abstract: A battery monitoring apparatus that senses battery conditions such as low battery charge, end of battery capacity, and end of battery life, and responds by taking actions such as sending messages to a remote site and/or powering down. A rechargeable battery is coupled to one or more power-consuming electrical components, including battery monitoring equipment. The battery monitoring equipment senses battery charge. In response to a low-battery-charge condition, the battery monitoring equipment transmits a battery status message to a remote site and powers-down some of the electrical components. Whenever the battery nears the end of its capacity, the monitoring equipment powers down all electronic components and awaits the application of external power. The invention also tracks the time required for the battery charge to deplete. Charge duration decreases over time, and whenever it reaches a predetermined minimum, the battery monitoring equipment transmits a representative status message to the remote site.

Abstract: In some implementations, a computer-implemented method includes storing a plurality of acceleration profiles in a mobile device; receiving accelerometer data from an accelerometer in the mobile device; correlating the accelerometer data with one accelerometer profile in the plurality of accelerometer profiles; and activating a user application of the mobile device that is associated with the correlated accelerometer profile. Each acceleration profile can correspond to a sequence of acceleration forces a mobile device would be subjected to when carried with a user during an activity that corresponds to the correlated acceleration profile.

Abstract: Various computing center control and cooling apparatus and methods are disclosed. In one aspect, a method of controlling plural processors of a computing system is provided. The method includes monitoring activity levels of the plural processors over a time interval to determine plural activity level scores. The plural activity level scores are compared with predetermined processor activity level scores corresponding to preselected processor operating modes to determine a recommended operating mode for each of the plural processors. Each of the plural processors is instructed to operate in one of the recommended operating modes.

Abstract: Systems and methods of operating a computing system may involve identifying a plurality of state values, wherein each state value corresponds to a computing thread associated with a processor. An average value can be determined for the plurality of state values, wherein a determination may be made as to whether to grant a frequency boost request based at least in part on the average value.