Abstract: An electronic apparatus is provided. The electronic apparatus includes a serial advanced technology attachment (SATA) physical layer, a clock generator and a control unit. The SATA physical layer is configured to provide connection with an SATA device and perform data transmission with the SATA device is performed at a first clock frequency. The clock generator is configured to provide a clock signal having the first clock frequency to the SATA physical layer. When at least one specific event is detected by the control unit, the control unit controls the clock generator to provide the clock signal having a second clock frequency to the SATA physical layer, so that the SATA physical layer performs data transmission with the SATA device at the second clock frequency. The second clock frequency is lower than the first clock frequency.

Abstract: A method is provided in one example embodiment and includes storing secure boot variables in a baseboard management controller; and sending the secure boot variables to a basic input/output system (BIOS) during a power on self-test, where the BIOS utilizes the secure boot variables during runtime to authenticate drivers and an operating system loader execution. In particular embodiments, the secure boot variables may be included in a white list, a black list, or a key list and, further, stored in erasable programmable read only memory.

Abstract: An approach is provided for collaborative context data sensing and communications. A context platform determines context data from a plurality of devices. The context platform processes and/or facilitates a processing of the context data to determine scheduling information for causing, at least in part, a sensing, a transmission, or a combination thereof of additional context data by at least one of the plurality of devices. The context platform then determines the additional context data based, at least in part, on the scheduling information.

Abstract: Various methods and apparatus for managing signals between a processor and a memory device are disclosed. In one aspect, a method of managing signals between a processor and a memory device wherein the processor and the memory device are operatively coupled by a data signal path and a clock signal path is provided. The method includes setting the skew between the data signal path and the clock signal path away from a spectral peak of a phase jitter transfer function.

Abstract: Aspects of the subject disclosure relate to a storage device including a flash memory, a controller coupled to the flash memory, wherein the controller is configured to store data to the flash memory and a power arbiter unit coupled to the controller and to the flash memory via a plurality of flash channels, wherein the power arbiter unit is configured to receive a plurality of power requests via one or more of the plurality of flash channels and process the plurality of power requests based on a respective priority identifier associated with each of the plurality of power requests. Additionally, a computer-implemented method and power arbiter unit (PAB) are provided.

Abstract: In some implementations, a computer-implemented method includes storing a plurality of acceleration profiles in a mobile device; receiving accelerometer data from an accelerometer in the mobile device; correlating the accelerometer data with one accelerometer profile in the plurality of accelerometer profiles; and activating a user application of the mobile device that is associated with the correlated accelerometer profile. Each acceleration profile can correspond to a sequence of acceleration forces a mobile device would be subjected to when carried with a user during an activity that corresponds to the correlated acceleration profile.

Abstract: Embodiments of the invention include an IC that includes a core used for ordinary operation and a thin power circuit. The thin power circuit can be configured to use very little power. The IC can also include a digital interface and a connection thereto. The IC can initiate transition to low power mode during which the core and various I/O pads can be shut down. However, the thin power circuit can be kept powered up. The thin power circuit can monitor the digital interface for a predefined wake up signal. When the wake up signal is detected, the thin power circuit can power up the core and any powered down I/O pads. The thin power circuit can also include a dedicated power on reset (POR) cell. This POR cell can be distinct than other POR cells used for the IC and can be specifically designed to for efficient operation.

Abstract: Described herein is a system having a multi-host SATA controller (102) configured to provide communication and control between two or more independent host processors (104) and a single SATA device (108). In one implementation, the multi-host SATA controller (102) includes the device switching layer (206), the device control layer (208), the link layer (210), and the physical layer (212). The device switching layer (206) allows the host processors (104) to issue commands concurrently rather than in sequential order. For this, the device switching layer (206) has independent set of host device registers (214) corresponding to each of the host processors (104). The device switching layer (206) also has independent DMA engines (216) to perform a command pre-fetching from respective host system memories (105). Further, a command switch engine (220) may arbitrate commands in case both the host processors (104) wish to access the SATA device (108) simultaneously.

Abstract: A wireless mobile device includes a configurable co-processor core(s). The wireless mobile device also includes a multi-core central processing unit coupled to a memory and the configurable co-processor core(s). The multi-core central processing unit may select from a set of hardware accelerators according to a user's use pattern. The wireless mobile device also includes a hardware controller that reconfigures the configurable co-processor core(s) according to a selected hardware accelerator.

Abstract: A memory interface includes circuitry configured for applying a variable delay to a portion of a data signal and applying a variable delay to a data strobe. The delayed data strobe samples the delayed portion of the data signal. Delayed portions of the data signal are spaced away from non-delayed portions of the data signal by alternating the routing of delayed bits and non-delayed bits of the data signal. A training block determines and sets a value of the variable delay corresponding to a largest value of a number of recorded eye aperture widths.

Abstract: A serial bus network includes a voltage regulator, a plurality of power switches, and a voltage monitor. The voltage regulator provides power to a plurality of serial buses. Each of the serial buses provides power from the voltage regulator to a device coupled to the serial bus. Each of the power switches switches power from the voltage regulator to one of the serial buses, and includes an input terminal coupled to a voltage regulator output, and an output terminal coupled to one of the serial buses. The voltage monitor is coupled to the voltage regulator and to the output terminal of each of the power switches. The voltage monitor compares bus voltages at the output terminals of the power switches, identifies a lowest of the bus voltages, and adjusts the voltage regulator output voltage such that the identified lowest of the bus voltages is within a predetermined operational voltage range.

Abstract: A server is provided in the present disclosure, and the server includes a power module, a motherboard circuit, and a power management circuit. The power management circuit is coupled to the motherboard circuit and the power module. The motherboard circuit receives a remote control signal through a network module and outputs a power-off command to the power management circuit according to the remote control signal. The power management circuit causes the power module to stop supplying power to the motherboard circuit for a predetermined time according to the power-off command. After the predetermined time, the power management circuit causes the power module to supply power again to the motherboard circuit to execute an initialization procedure.

Abstract: An information handling system includes a processor, a controller hub, a shared higher bandwidth path coupling the processor to the controller hub, and an exclusive lower bandwidth path coupling the processor to the controller hub. The processor communicates system management information over the bandwidth path in response to a first set of criteria and communicates the information over the lower bandwidth path in response to the second set of criteria.

Abstract: A system and method of managing power may include determining a power state based on a first power management request from a first operating system executing on a mobile platform and a second power management request from a second operating system executing on the mobile platform. The first operating system and one or more components of the mobile platform can define a first virtual machine, and the second operating system and one or more components of the mobile platform can define a second virtual machine. In addition, the power state may be applied to the mobile platform.

Abstract: In a wired data telecommunication network power sourcing equipment (PSE) coupled to a powered device (PD) carries out an inline power discovery process to verify that the PD is adapted to receive inline power, then a plurality of classification cycles are carried out to convey a series of inline power classes back to the PSE. The series of inline power classes may all be the same, in which case the PD is legacy equipment and is adapted to receive the power level corresponding to that class. If they are not all the same, information is thus conveyed to the PSE which may, for example, correspond to a specific power level to be applied or to other information.

Abstract: A method for executing a Basic Input Output System (BIOS) tool program in a non-System Management Interrupt (SMI) mechanism is applicable to a computer and includes: bi-directionally transmitting, by an ACPI ASL module and a service module, a corresponding trigger signal; bi-directionally transmitting, by the service module and a driver, the trigger signal; bi-directionally transmitting, by the driver and a real-time service module of a BIOS, the trigger signal; and performing, by the BIOS, event processing according to the trigger signal to obtain a processing result, or performing, by the BIOS, logic operation on the data to obtain operation data.

Abstract: A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

Abstract: A voltage conversion circuit such as a buck regulator circuit has a plurality of switches coupled to a voltage source; a slab inductor having a length, a width and a thickness, where the slab inductor is coupled between the plurality of switches and a load and carries a load current during operation of the plurality of switches. The voltage conversion circuit can also include means to reduce or cancel a detrimental effect of other wires on same chip, such as a power grid, that conduct a return current and thereby degrading the functionality of this slab inductor. In one embodiment the wires can be moved further away from the slab inductor and in another embodiment magnetic materials can be used to shield the slab inductor from at least one such interfering conductor.

Abstract: A method is disclosed to operate a voltage conversion circuit such as a buck regulator circuit that has a plurality of switches coupled to a voltage source; a slab inductor having a length, a width and a thickness, where the slab inductor is coupled between the plurality of switches and a load and carries a load current during operation of the plurality of switches; and a means to reduce or cancel the detrimental effect of other wires on same chip, such as a power grid, potentially conducting return current and thereby degrading the functionality of this slab inductor. In one embodiment the wires can be moved further away from the slab inductor and in another embodiment magnetic materials can be used to shield the slab inductor from at least one such interfering conductor.

Abstract: A storage device including a communications interface configured to receive data and power, a plurality of disk drives configured to be powered only by the power received by the communications interface, a controller configured to configure the plurality of disk drives as a redundant array of independent disks, a power regulator configured to transmit the received power from the communications interface to the plurality of disk drives, and a peak current reduction circuit configured to reduce peak current usage by the plurality of disk drives.