Abstract: According to one embodiment of the invention, an integrated circuit device at least one compute engine and a control unit. Coupled to the compute engine(s), the control unit is adapted to dynamically control an energy-efficient operating setting of at least one power management parameter for the integrated circuit device after execution of Basic Input/Output System (BIOS) has already completed.

Abstract: Embodiments of the present disclosure are directed to, among other things, managing power of one or more data storage devices. In some examples, a storage service may obtain a schedule associated with enabling different storage devices at different times. The storage service may also identify a request of a batch of requests for accessing the storage devices. In some cases, the storage service may also determine which storage device to activate based at least in part on the schedule and/or the request. Further, the storage service may manage power of a storage device based at least in part on the determination of which storage device to activate.

Abstract: An information processing apparatus operable in a standby mode and in a sleep mode. The information processing apparatus comprising a sleep unit and, a power-off unit. The sleep unit configured to shift the information processing apparatus into the sleep mode if a first time has elapsed in the standby mode. The power-off unit configured to turn off the power supply of the information processing apparatus if a second time has elapsed in the sleep mode and configured to turn off the power supply of the information processing apparatus at a specified time. The power-off unit configured to turn off the power supply of the information processing apparatus without waiting for the second time if the information processing apparatus has been started after the time specifying power-off processing.

Abstract: There is provided a method of managing power in a multi-core data processing system having two or more processing cores, comprising determining usage characteristics for the two or more processing cores within the multi-core processing unit, and dependent on the determined usage characteristics, adapting a frequency or voltage supplied to each of the two or more processing cores, and/or adapting enablement signals provided to each of the two or more processing cores. There is also provided an apparatus for carrying out the disclosed method.

Abstract: A method is disclosed to operate a voltage conversion circuit such as a buck regulator circuit that has a plurality of switches coupled to a voltage source; a slab inductor having a length, a width and a thickness, where the slab inductor is coupled between the plurality of switches and a load and carries a load current during operation of the plurality of switches; and a means to reduce or cancel the detrimental effect of other wires on same chip, such as a power grid, potentially conducting return current and thereby degrading the functionality of this slab inductor. In one embodiment the wires can be moved further away from the slab inductor and in another embodiment magnetic materials can be used to shield the slab inductor from at least one such interfering conductor.

Abstract: A method is disclosed to operate a voltage conversion circuit such as a buck regulator circuit that has a plurality of switches coupled to a voltage source; a slab inductor having a length, a width and a thickness, where the slab inductor is coupled between the plurality of switches and a load and carries a load current during operation of the plurality of switches; and a means to reduce or cancel the detrimental effect of other wires on same chip, such as a power grid, potentially conducting return current and thereby degrading the functionality of this slab inductor. In one embodiment the wires can be moved further away from the slab inductor and in another embodiment magnetic materials can be used to shield the slab inductor from at least one such interfering conductor.

Abstract: An integrated circuit (IC) stack device for multiple active vertically stacked cores is disclosed. The IC stack device can include a primary IC having a first set of cores, and a supplementary IC interfaced with the primary IC having a second set of cores. The IC stack device can also include a peripheral component connection located such that the primary IC is between the peripheral component connection and the supplemental IC. The IC stack device can include control logic configured to route, in a primary mode, signals from a particular core of the first set of cores to a data bus. The control logic can route, in a secondary mode, signals from a particular core of the second set of cores to a data bus. The control logic can route, in a dual mode, signals from both of the particular cores to a data bus.

Abstract: A method and an apparatus are provided. The apparatus is a hardware module that controls a power mode of a plurality of modules. The apparatus receives an indication of a desired operational frequency. Based on the received indication, the apparatus determines to switch from a first power mode associated with a first set of modules to a second power mode corresponding to the desired operational frequency and associated with a second set of modules. The apparatus enables modules in the second set of modules that are unassociated with the first power mode, stops traffic through the plurality of modules upon expiration of a time period after enabling the modules in the second set of modules that are unassociated with the first power mode, routes traffic through the second set of modules, and disables modules in the first set of modules that are unassociated with the second power mode.

Abstract: A system and method are provided for regulating a supply voltage of a device. The method includes the steps of determining whether a supply voltage for an analog multiplexor is below a threshold voltage. If the supply voltage for the analog multiplexor is below the threshold voltage, then the method includes the step of shorting the supply voltage to an output of the analog multiplexor. However, if the supply voltage for the analog multiplexor is above or equal to the threshold voltage, then the method includes the step of transmitting at least one input signal coupled to the analog multiplexor to the output of the analog multiplexor. A system configured to implement the method may include a power management integrated circuit configured to generate a supply voltage for a device and a device that includes a self-powered analog multiplexor with voltage sensing bypass switch.

Abstract: A cable for providing electric power from a power source to a mobile device, the cable having a first connector at a first end of the cable for connecting the cable to a mobile device and with a second connector at a second end for connecting the cable to the power source, wherein the cable comprises a memory module for backup and bidirectional transfer of data to and from the mobile device.

Abstract: A method is disclosed to operate a voltage conversion circuit such as a buck regulator circuit that has a plurality of switches coupled to a voltage source; a slab inductor having a length, a width and a thickness, where the slab inductor is coupled between the plurality of switches and a load and carries a load current during operation of the plurality of switches; and a means to reduce or cancel the detrimental effect of other wires on same chip, such as a power grid, potentially conducting return current and thereby degrading the functionality of this slab inductor. In one embodiment the wires can be moved further away from the slab inductor and in another embodiment magnetic materials can be used to shield the slab inductor from at least one such interfering conductor.

Abstract: Systems and a method for controlling power of a device with power management software are described. In one embodiment, a computer implemented method initiates power control having ON-OFF keying to control power consumption of a device for energy efficiency and energy conservation. An ON-OFF period of the ON-OFF keying for the device is computed. The method sets a target frequency, a target supply voltage, and a power gate control for the device based on the ON-OFF keying.

Abstract: Powering a data storage device (DSD) including at least a first storage tier and a second storage tier. A current used by the DSD is monitored and it is determined whether the current exceeds a current threshold. A throttle signal is asserted to reduce power used by the first storage tier when it is determined that the current exceeds the current threshold.

Abstract: A power management device is adapted to reduce power consumption, particularly in battery-powered applications such as within a node in a utility network (e.g., in a gas, water, or other utility application). In one example, a low-current voltage regulator provides power to a processor during low-power “sleep” states. A high-current voltage regulator provides power to the processor, metrology devices and/or a radio during “awake” states. A buck-boost device may provide power to a transmitter during radio frequency (RF) transmissions. A max device may determine a greater of voltages output by a battery and the buck-boost device, and use the higher to power the high-current voltage regulator. The power management device may include a state machine, which may include several states and operations to perform within each state. In one state, the processor enters a sleep state prior to recovery of battery voltage after a transmission state.

Abstract: The invention discloses system and method of temporary secure boot process of an electronic device. The method comprises: generating a first token according to an identification data of the electronic device; sending a request along with the first token to a service provider, the request corresponding to a boot package; receiving a second token and a boot package from the service provider; verifying the second token and the boot package; and executing the boot package according to verification result.

Abstract: In accordance with the present disclosure, a system and method for providing scalable and modular power infrastructure outside of usable rack space is described. The system may include a chassis configured to mount on the side of a rack. A power cable interface box (PCIB) may be disposed within the chassis, and the PCIB may receive alternating current (AC) power. The system may further include at least one power supply unit disposed within a slot of the chassis, with the at least one power supply unit receiving AC power from the PCIB and outputting direct current (DC) power to a busbar. The system may also include a battery back-up unit (BBU) element disposed within the chassis. The BBU element may charge from and discharge to the busbar.

Abstract: A mobile device communicates with an authenticator affiliated with a recharging facility, to identify itself. To confirm that the mobile device is connected to the correct facility, the authenticator instructs the mobile device to draw electrical charge according to an identifiable pattern. Upon detecting a charge being drawn according to that pattern, the authenticator has confirmation that the identified device is connected to the facility, and permits the charging to proceed. The amount of electricity drawn during the charging procedure can be metered, and then billed to a party associated with the identified mobile device.

Abstract: An information processing apparatus includes a nonvolatile memory, a volatile memory, and a process control section. A startup program to be required when starting up the information processing apparatus has previously been stored in the nonvolatile memory. When a command to start up the apparatus is received, it is determined whether or not the startup program is present in the volatile memory. When the startup program is absent, the startup program is loaded from the nonvolatile memory into the volatile memory. Thereafter, when a command to turn off the power of the information processing apparatus is received, supply of power to other components of the information processing apparatus than the volatile memory is stopped while maintaining supply of power to the volatile memory, thereby to shutdown the power of the information processing apparatus.

Abstract: An electronic system is disclosed, which may include a phase pipeline, a data pipeline, an input phase selector, and an output phase selector. The phase pipeline may have latches clocked by a clock signal, and designed to propagate phase signals from a phase input to a phase output. The data pipeline may have latches clocked by the phase pipeline clock signal, and designed to propagate data from a data input to a data output. The input phase selector may be designed to provide an inverted or a non-inverted copy of data from a data input, in response to a value at the phase input, to the data pipeline data input. The output phase selector may be designed to provide an inverted or a non-inverted copy of data from the data pipeline output to an output phase selector data output, in response to a phase pipeline output value.

Abstract: Systems and methods that enable a reduction of the power consumption involved in measuring a user's affective response to content with a sensor belonging to a wearable device. The reduction in power consumption is achieved by utilizing eye tracking to determine when a user is paying attention to the content, and accordingly setting a mode of operation of the wearable device to measure the user. Thus, by using different modes of operation, which are characterized by different energy consumption rates, the total power consumption of the wearable device may be reduced, essentially without loss of relevant measurements.