Patents Examined by Dharti H. Patel
  • Patent number: 11368016
    Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include electrostatic discharge (ESD) protection circuit structures. The ESD protection circuit structures may be formed in regions other than the region that the IGFETs are formed as well as in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming ESD protection circuit structures in regions below the IGFETs, an older process technology may be used and device size may be decreased. Furthermore, planar IGFETs of FinFETs may be formed in other regions to decrease device size and improve costs.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: June 21, 2022
    Assignee: Mavagail Technology, LLC
    Inventor: Darryl G. Walker
  • Patent number: 11362504
    Abstract: Circuits and methods for protecting against over-current conditions of switches are described. Over-current conditions can damage switches and the circuits they connect. Some embodiments of the present application provide a sense switch in parallel with the load switch. The sense switch is smaller than the load switch, and is used to sense an over-current condition of the load switch. The sense switch can remain on even when the load switch is turned off in response to detection of an over-current condition.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: June 14, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: Jofrey Generalao Santillan, David Aherne
  • Patent number: 11362515
    Abstract: The present invention discloses an electrostatic discharge protection circuit having false-trigger prevention mechanism. A RC circuit, including an input control terminal, is coupled between an electrostatic discharge input terminal for receiving an input power and a ground terminal. An inverter includes a P-type transistor circuit, including P-type transistors coupled between the electrostatic discharge input terminal and an output control terminal in series and having an internal connection terminal between two of the P-type transistors, and an N-type transistor, coupled between the output control terminal and the ground terminal. Gates of the P-type and N-type transistors are controlled by the input control terminal A switch transistor, having the gate controlled by the input control terminal, is coupled between the internal connection terminal and the ground terminal.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: June 14, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shih-Hsin Liao, Jyun-Ren Chen, Tay-Her Tsaur, Po-Ching Lin
  • Patent number: 11355292
    Abstract: A system may include a relay device that includes armatures associated with phases of voltage signals. The system may also include relay coils, such that each relay coil may receive a respective voltage that magnetizes a respective relay coil, thereby causing the respective armature to move from a respective first position to a respective second position. The system may also include a control system that receive an indication that a fault condition is present, identify a first phase of the phases of voltage signals that is expected to be the next phase of the phases to cross zero, and send a signal to the relay device in response to identifying the first phase. The signal is configured to cause a first relay coil of the relay coils to energize or deenergize.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: June 7, 2022
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: David Elmiger, Andrew J. Jaap, Kyle B. Adkins, Randall S. Langer
  • Patent number: 11355490
    Abstract: A semiconductor structure corresponds to a first diode and a second diode connected in series. A first well region is on a first deep well region. Two second well regions are at two sides of the first well region respectively. A first doping region and a second doping region are on the first well region. A first isolation region is between the first doping region and the second doping region. A third well region is on a second deep well region. Two fourth well regions are at two sides of the third well region respectively. A third doping region and a fourth doping region are on the third well region. A second isolation region is between the third doping region and the fourth doping region. The second doping region and third doping region are connected. The second deep well region is separated from the first deep well region.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: June 7, 2022
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu Lin, Chun-Cheng Chen, Wen-Tai Wang
  • Patent number: 11355927
    Abstract: A device is disclosed herein. The device includes an electrostatic discharge (ESD) detector, a bias generator, and an ESD driver including at least two transistors coupled to each other in series. The ESD detector is configured to detect an input signal and generate a detection signal in response to an ESD event being detected. The bias generator is configured to generate a bias signal according to the detection signal. The at least two transistors are controlled according to the bias signal and a logic control signal, and the input signal is applied across the at least two transistors.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Yu-Ti Su, Chia-Wei Hsu, Ming-Fu Tsai, Shu-Yu Su, Li-Wei Chu, Jam-Wem Lee, Chia-Jung Chang, Hsiang-Hui Cheng
  • Patent number: 11349414
    Abstract: An apparatus and a method for monitoring the relative relationship between the wafer and the chuck is provided, especially for monitoring whether the wafer is sticky on the chuck when the wafer is de-chucked. The lift pins may be extended outside the chuck to separate the wafer and the chuck when the wafer is de-chucked. By detecting the capacitance between the de-chucked wafer and the chuck, especially by comparing the detected capacitance with the capacitance that the wafer is held by the chuck, one may determine whether the wafer is sticky on the chuck, or even whether the wafer is properly supported by the lift pins. Accordingly, an early alarm may be issued if the wafer is sticky or improperly removed. Besides, by controlling a switch electrically connected to a lift pin that contacted the wafer, the charges at the wafer may be eliminated.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: May 31, 2022
    Assignee: ADVANCED ION BEAM TECHNOLOGY, INC.
    Inventors: Te-Min Wang, Yu-Ho Ni, Chun-Chieh Lin, Chien-Chung Hou, Cheng-Mao Chien
  • Patent number: 11346906
    Abstract: A magnetic resonance system may include a magnetic resonance magnet and a storage container configured to accommodate the magnetic resonance magnet. The storage container may also contain an endothermic liquid. The magnetic resonance system may further include a ramping-down device configured to trigger releasing electric energy by the magnetic resonance magnet. The first ramping-down device may include an electric energy consumption device configured to consume at least a portion of the released electric energy by the magnetic resonance magnet.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: May 31, 2022
    Assignee: SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.
    Inventor: Jianfeng Liu
  • Patent number: 11349304
    Abstract: Embodiments of the disclosure provide a circuit structure and method to control electrostatic discharge (ESD) events in a resistor-capacitor (RC) circuit. Circuit structures according to the disclosure may include a trigger transistor coupled in parallel with the RC circuit, and a gate terminal coupled to part of the RC circuit. A mirror transistor coupled in parallel with the RC circuit transmits a current that is less than a current through the trigger transistor. A snapback device has a gate terminal coupled to a source or drain of the mirror transistor, and a pair of anode/cathode terminals coupled in parallel with the RC circuit. A current at the gate terminal of the snapback device, derived from current in the mirror transistor, controls an anode/cathode current flow in the snapback device.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: May 31, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Alain F. Loiseau, Robert J. Gauthier, Jr., Souvick Mitra, You Li, Meng Miao, Wei Liang
  • Patent number: 11342735
    Abstract: The invention relates to a novel approach for the protection of electrical circuits from ground faults and parallel and series arc faults in a fully solid-state circuit configuration. Solid-state circuits and methods of use are described that provide the key functions of low-voltage DC power supply, mains voltage and current sensing, fault detection processing and high voltage electronic switching.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: May 24, 2022
    Inventors: Mark Telefus, Bradley Larson, Harry Rodriguez, Stephen C. Gerber
  • Patent number: 11333691
    Abstract: According to some aspects of the present disclosure, power modules having current sensing circuits, and corresponding sensing methods, are disclosed. Example power modules include a printed circuit board (PCB) having a PCB trace, a first sense terminal coupled to the PCB trace at a first location, and a second sense terminal coupled to the PCB trace at a second location such that a resistance between the first and second sense terminals is defined by a resistance of the PCB trace between the first location and the second location. The power module further comprises a control coupled to the first sense terminal and the second sense terminal, the control adapted to measure a voltage between the first sense terminal and the second sense terminal and determine a current through the PCB trace based on the measured voltage and the resistance between the first sense terminal and the second sense terminal.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: May 17, 2022
    Assignee: Astec International Limited
    Inventors: Mao Xi Xiang, Jian Feng Lv, Chen Chen Zheng, Qian Feng
  • Patent number: 11329438
    Abstract: A method of ensuring power delivery in a universal serial bus (USB) interface between a device and a counterpart device, the device including a port controller and a USB receptacle. The method includes the port controller attempting to detect an abnormal state in which a leakage current occurs in the USB receptacle using at least one pin of the USB receptacle; and when the abnormal state is detected, the port controller turning OFF a switch connected between a power pin of the USB receptacle and an internal circuit of the device, and determining to enter an unattached state of being separated from the counterpart device.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: May 10, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Je-Kook Kim
  • Patent number: 11328872
    Abstract: An LC composite component includes a non-magnetic substrate, a magnetic layer with magnetism, capacitors, inductors, and core parts with magnetism. The non-magnetic substrate includes a first surface and a second surface on a side opposite to the first surface. The magnetic layer is disposed to face the first surface of the non-magnetic substrate. The inductors and the capacitors are disposed between the first surface of the non-magnetic substrate and the magnetic layer. The core parts are disposed between the first surface of the non-magnetic substrate and the magnetic layer and connected to the magnetic layer. The thickness of the core parts is 1.0 or more times the thickness of the magnetic layer in a direction perpendicular to the first surface of the non-magnetic substrate, and each of the magnetic layer and the core parts contains magnetic metal particles and resin.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: May 10, 2022
    Assignee: TDK CORPORATION
    Inventors: Yoshihiro Shinkai, Yuichiro Okuyama, Tomoya Hanai, Yusuke Ariake, Isao Kanada, Takashi Ohtsuka
  • Patent number: 11328907
    Abstract: According to one embodiment, an electrostatic chuck includes a ceramic dielectric substrate, a base plate, and a first electrode layer. The ceramic dielectric substrate has a first major surface and a second major surface. The first electrode layer is provided inside the ceramic dielectric substrate and connected to a high frequency power supply. The first electrode layer is provided between the first major surface and the second major surface. The first electrode layer has a first surface and a second surface. A surface roughness of the second surface is larger than a surface roughness of the first surface.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: May 10, 2022
    Assignee: Toto Ltd.
    Inventors: Yutaka Momiyama, Hitoshi Sasaki
  • Patent number: 11329456
    Abstract: An ionic wind generator and an electronic device having a heat dissipation function using the same are proposed. The ionic wind generator includes a power module; a first electrode configured to receive power from the power module by being connected to the power module to become an emitter electrode; and a second electrode spaced apart from the first electrode and grounded and at the same time connected to the power module to become a counter electrode. In addition, the first electrode is configured as a carbon brush including multiple carbon fibers. Accordingly, in the ionic wind generator, the emitter electrode is configured as the carbon brush having multiple carbon fibers.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: May 10, 2022
    Assignee: LG ELECTRONICS INC.
    Inventors: BongJun Kim, Jae Hyun Oh, Changhee Lee, MinWoo Jeong, Minjae Park
  • Patent number: 11322927
    Abstract: A dropout recloser is capable of in accordance with its operating programming after a predetermined number of fault interrupting operations, e.g., 1, 2, 3 or more but typically 3, to drop out of a cutout and hang freely in a hinge contact of the cutout providing sectionalization with an observable visible gap. The recloser includes fault interrupting and reclosing components, a drop out mechanism and a controller. The drop out mechanism may include a bi-stable actuator to affect fault interrupting operation and dropout operation. The device may include motion limiting structures. The recloser may have a number of operating modes or sequences.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: May 3, 2022
    Assignee: S&C Electric Company
    Inventors: Richard G. Smith, Yujian Zhou, Jorge Montante, Alejandro Montenegro, Michael Ross
  • Patent number: 11322915
    Abstract: Methods and assemblies to stabilize and reduce an electric field in an environment are provided that include an elongated member and a head member. The head member is coupled to the elongated member. The head member includes a floating electrode, a ground electrode, and an insulator portion. The ground electrode spaced apart from the floating electrode. The ground electrode is in communication with the elongated member to receive a charge with a polarity of a earth system. The insulator portion is positioned between the floating and ground electrodes to insulate the floating electrode from the ground electrode. The floating electrode induces an electrical charge from the environment surrounding the head member. The floating electrode balances an existing charge on the ground electrode using an electromagnetic induction to collect a plurality of charges in the environment such that the floating and ground electrodes generate a balanced electric field.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: May 3, 2022
    Inventor: Armando Chifarelli
  • Patent number: 11322935
    Abstract: An ESD protection circuit is disclosed. The ESD protection circuit is coupled between a first node and a second node that is coupled to an input of a functional circuit. A first protection circuit is coupled to the first node. The circuit further includes a first path and a second path. The first path includes a second protection circuit that is coupled to the second node, and is AC coupled to the first node. A second circuit path includes a third protection circuit, a resistor coupled between the third protection circuit and the first node, and a switch having a first terminal coupled to the resistor and the third protection circuit. A shunt circuit includes a transistor having a gate terminal coupled to the second terminal of the switch. The transistor, when activated, shunts current from the second node to ground.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: May 3, 2022
    Assignee: Apple Inc.
    Inventors: Farzan Farbiz, Jaeduk Han, Praveen R. Singh
  • Patent number: 11322929
    Abstract: An apparatus for detecting an open neutral condition in a split phase power system is described. The apparatus includes two powered lines providing output electricity to an electrical distribution system and a shared neutral line providing a grounded neutral to the first and second powered lines. The apparatus is configured for detecting when an open neutral condition is present in the split phase power system by determining when a power current is present on one or both of the first and second powered lines while a return current is not present on the neutral line; and in response to detecting that the open neutral condition is present, causing an interrupter to interrupt the power supplied by the first and second powered lines or to generate a signal indicating an open condition.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: May 3, 2022
    Assignee: Southwire Company, LLC
    Inventors: Donald Paul Oldham, Jr., Hamze Moussa
  • Patent number: 11316341
    Abstract: Disclosed are a surge protection power supply clamping circuit, a chip and a communication terminal. The power supply clamping circuit comprises at least one driving unit and discharging unit; the discharging units are connected to the corresponding driving units respectively, and the driving units are connected to the same time delay unit respectively; the time delay units and the discharging units are connected to a power supply voltage and a ground line respectively. The driving units or the discharging units are sequentially controlled in the power supply voltage wiring direction, so that the sum values of an equivalent conduction resistance and an equivalent metal wiring resistance of respective discharging units are the same, and therefore, the uneven conduction of an NMOS transistor caused by different metal wiring resistances due to different metal wiring lengths of the NMOS transistor of each discharging unit can be counteracted.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: April 26, 2022
    Assignee: VANCHIP (TIANJIN) TECHNOLOGY CO., LTD.
    Inventor: Sheng Lin