Abstract: The present disclosure provides an over-voltage protection device. The over-voltage protection device includes a substrate, a stack structure disposed over the substrate. The stack structure includes a first insulation structure, a second insulation structure, and a conductive layer. The conductive layer is disposed on the first insulation structure, and the second insulation structure is disposed on the conductive layer. The second insulation structure has an insulation air gap, which has an upper width greater than a lower width.

Abstract: A tuned single-coil inductor is implemented between a signal driver output and external contact of an ESD-protected integrated circuit (IC) die and more specifically between the parasitic capacitances of the signal driver and the contact-coupled ESD (electrostatic discharge) element to form a Pi (?) filter that enhances signaling bandwidth at the target signaling rate of the IC die. The signal driver may be implemented with output-stage data serialization circuitry disposed in series between source terminals of a thick-oxide drive transistor and a power rail to avoid explicit level-shifting circuitry between the relatively low core voltage domain and relatively high I/O voltage domain.

Abstract: An electrostatic discharge (ESD) protection circuit is provided, which includes multiple ESD clamping circuits and a shunt circuit. The multiple clamping circuits comprise multiple transistors, respectively. The multiple transistors are coupled in series between a first power line and a second power line. A shunt circuit is coupled with a first terminal and a control terminal of a first transistor of the multiple transistors. The shunt circuit is configured to conduct the first terminal of the first transistor to the control terminal of the first transistor during a period of an ESD event to raise a voltage of the control terminal of the first transistor. The shunt circuit insulates the first terminal of the first transistor from the control terminal of the first transistor during a period outside the period of the ESD event.

Abstract: In an output circuit of a semiconductor integrated circuit device, an output transistor is placed apart from an ESD protection diode connected to an external output terminal, and a protection resistance is placed between them. The protection resistance is formed as a plurality of separate resistance regions, and taps supplying a power supply voltage to a substrate or a well are formed between the resistance regions. Noise applied to the external output terminal is attenuated by the protection resistance before reaching the output transistor and absorbed through the taps.

Abstract: An electrostatic discharge (ESD) protection circuit including a detection circuit, a voltage-divider element, and a discharge element is provided. The detection circuit is coupled between a first power line and a second power line. In response to an ESD event, the detection circuit enables a turn-on signal. The voltage-divider element is coupled between the first power line and a third power line and receives the turn-on signal. The discharge element is coupled between the second and third power lines. In response to the turn-on signal being enabled, the first discharge element discharges an ESD current.

Abstract: A nanosecond pulser system is disclosed. In some embodiments, the nanosecond pulser system may include a nanosecond pulser having a nanosecond pulser input; a plurality of switches coupled with the nanosecond pulser input; one or more transformers coupled with the plurality of switches; and an output coupled with the one or more transformers and providing a high voltage waveform with a amplitude greater than 2 kV and a frequency greater than 1 kHz based on the nanosecond pulser input. The nanosecond pulser system may also include a control module coupled with the nanosecond pulser input; and an control system coupled with the nanosecond pulser at a point between the transformer and the output, the control system providing waveform data regarding an high voltage waveform produced at the point between the transformer and the output.

Abstract: An ESD protection circuit that includes a clamp path including two clamp transistors and a GIDL detection circuit for detecting GIDL current conditions in the ESD protection circuit. The GIDL detection circuit generates a signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a clamp transistor of the clamp path to increase the conductivity of the clamp transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least through a portion of the clamp path when the second clamp transistor is nonconductive where no ESD current is being discharged through the clamp path.

Abstract: The aim of the invention is to detect an arc in an assembly for transmitting a direct voltage. This aim is achieved by a communication transformer having a primary winding and a secondary winding, the secondary winding being connected to a transmitting device, which is designed to impress a communication signal onto the secondary winding of the communication transformer, and the primary winding being connected to one of the direct voltage lines in order to feed a communication signal transformed by the communication transformer to one of the direct voltage lines. In order to detect, in the assembly, the arc signal caused by an arc, the secondary winding is connected to an arc detection unit, which is designed to detect an arc signal transformed by the communication transformer.

Abstract: The present disclosure provides electrostatic discharge circuits and structures and methods for operating the electrostatic discharge circuits and structures. A circuit includes a first transistor and a second transistor. The first transistor includes a drain, a source, a gate, and a bulk. The drain of the first transistor is connected to a first terminal. The source of the first transistor is connected to receive a first voltage. The gate and the bulk of the first transistor is connected to receive a second voltage. The second transistor includes a drain, a source, a gate, and a bulk. The source, the gate, and the bulk of the second transistor is connected to receive the second voltage. The drain of the second transistor is connected to the first terminal. In response to the terminal reaching a trigger voltage, the first transistor is configured to be turned on.

Abstract: A trigger circuit includes a first capacitor and a second capacitor connected in series, a control device and an output of the trigger circuit. The first capacitor is connected to a first voltage rail and to a common node. The second capacitor is connected to a second voltage rail and to the common node. The control device has a first terminal that is coupled to the common node and a control terminal to receive a control signal. The control signal may be decoupled from transients on the first voltage rail and the second voltage rail. The output of the trigger circuit is coupled to the common node.

Abstract: A circuit structure includes: a network of clamps; sense elements in series with the clamps and configured to sense a turn-on of at least one clamp of the network of clamps; and feedback elements connected to the clamps to facilitate triggering of remaining clamps of the network of clamps.

Abstract: Examples relate to an overvoltage protection circuit for a device interface adapted to convey at least electrical energy. The overvoltage protection circuit includes a first and a second terminal and a normally-on transistor. The normally-on transistor is electrically coupled to the first and second terminal. The overvoltage protection circuit further includes a control circuit configured to switch off the normally-on transistor as a function of at least one of a voltage at the first terminal and a voltage at the second terminal. Further examples relate to a device including an interface and an overvoltage protection circuit. The first terminal of the overvoltage protection circuit is electrically coupled to the interface.

Abstract: An ESD protection circuit is provided, including a negative ESD protection module and a positive ESD protection module, where the negative ESD protection module includes a first resistor, a charging capacitor, a first field effect transistor, and a second field effect transistor, and the positive ESD protection module includes a fourth field effect transistor. When a negative ESD event occurs, there is a comparatively large transient voltage at a gate of a P-type enhanced GaN power device relative to a source of the P-type enhanced GaN power device. Therefore, a displacement current from the source to the gate of the P-type enhanced GaN power device is generated on the charging capacitor. A voltage drop generated by the displacement current on the first resistor may enable the first field effect transistor and the second field effect transistor to form a path when the first field effect transistor is turned on.

Abstract: The present invention relates to an electrostatic protection circuit for protecting an internal circuit. The electrostatic protection circuit includes: a first circuit connected between a power pad and an input pad and configured to discharge a first electrostatic current; a second circuit connected between the input pad and a ground pad and configured to discharge a second electrostatic current; a third circuit connected between the power pad and the input pad and configured to discharge a third electrostatic current; a fourth circuit connected between the power pad and the ground pad and configured to discharge a fourth electrostatic current; a fifth circuit connected between the input pad and the ground pad and configured to discharge a fifth electrostatic current; and a sixth circuit connected between the ground pad and the power pad and configured to discharge a sixth electrostatic current.

Abstract: Provided is a static eliminator that efficiently eliminates static electricity from a tray of a droplet ejection device of a tray transport type. A static eliminator 20 includes a movable part 22 which is pushed by a tray 12 due to movement of the tray 12 and moves, and an ion generator 24 disposed on a movement path of the tray 12 and configured to generate ions according to the movement of the movable part 22.

Abstract: A superconducting magnet comprising: a field coil comprising high temperature superconducting material and having a joint; a bypass resistance comprising a non-superconducting conductive material, wherein the bypass resistance is electrically connected to the field coil on both sides of the joint; wherein the joint is openable to break the field coil such that current flowing in the superconductor flows though the bypass resistance in order to dump energy from the field coil, and wherein the superconducting magnet is configured to open the joint in response to detection of a quench in the magnet.

Abstract: The present disclosure provides an electrostatic protection circuit and a display panel, wherein the electrostatic protection circuit includes a first voltage reference unit configured to divide a voltage between an array substrate row driving signal line and a common electrode line once; a second voltage reference unit configured to divide the voltage between the array substrate row driving signal line and the common electrode line twice; and a charge releasing unit that adjusts charge distribution between the array substrate row driving signal line and the common electrode line based on reference voltages provided by the first voltage reference unit and the second voltage reference unit.

Abstract: An electronic control unit includes a microcontroller. The microcontroller includes a power supply pin configured to receive power and at least one input/output (I/O) pin. A voltage regulator includes a power input configured to connect to a power source and to a regulated power output connected to the power supply pin via an I/O fault protection circuit.

Abstract: An apparatus for detecting an open neutral condition in a split phase power system is described. The apparatus includes two powered lines providing output electricity to an electrical distribution system and a shared neutral line providing a grounded neutral to the first and second powered lines. The apparatus is configured for detecting when an open neutral condition is present in the split phase power system by determining when a power current is present on one or both of the first and second powered lines while a return current is not present on the neutral line; and in response to detecting that the open neutral condition is present, causing an interrupter to interrupt the power supplied by the first and second powered lines or to generate a signal indicating an open condition.

Abstract: A device includes an electrostatic discharge (ESD) protection switch and an ESD driver. The ESD driver is configured to receive a first voltage at a first terminal and receive a second voltage at a second terminal and includes a first trigger circuit and a first resistor. The first trigger circuit includes a first input terminal and a first output terminal. The first input terminal is configured to receive the first voltage. The first resistor is coupled between the first output terminal and the second terminal. When the first voltage received at the first terminal is a first overvoltage and a voltage difference between the first voltage and the second voltage is higher than a first voltage threshold, the ESD driver outputs a first trigger signal to turn on the ESD protection switch.