Abstract: A gate driver integrated circuit includes a high-side region that operates in a first voltage domain according to a first pair of supply terminals that include a first lower supply terminal and a first higher supply terminal; a low-side region that operates in a second voltage domain according to a second pair of supply terminals; at least one termination region that electrically isolates the high-side region from the low-side region; a first electrostatic device arranged in the high-side region and connected to the first pair of supply terminals; a second electrostatic device arranged in the low-side region and connected to the second pair of supply terminals; and a third electrostatic device connected to a lower supply terminal of the first pair of supply terminals and is coupled in series with the first electrostatic device.

Abstract: A device, system and method protects from overvoltages. A power control device includes a component (310) configured to be powered according to a duty cycle. The power control device includes a controller (330) configured to determine the duty cycle that places the component on or off. The power control device includes a comparator (335) configured to determine when the duty cycle is off and an overvoltage is being experienced by the component. When the duty cycle is off and the overvoltage is being experienced by the component, the comparator selects a circuit pathway (345, 350) including a clamping device (350).

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.

Abstract: The present disclosure relates to an ESD protection device (240) for a USB interface (210). The ESD protection device (240) comprises an ESD protection component (246) configured to limit a voltage applied to the USB interface (210) and at least one discharge resistor (244, 244.1, 244.2) configured to discharge an AC coupling capacitor (242) of the USB interface (210). The ESD protection component (246) and the discharge resistor (244, 244.1, 244.2) are incorporated in a single electronic component (245).

Abstract: An electrostatic protection device for protecting an input port of an electronic circuit. The electrostatic protection device includes a first stacked coil, a second stacked coil, and an input terminal, wherein the second stacked coil is inductively coupled to the first stacked coil. The first stacked coil comprises a first coil input connected to the input terminal, and a first coil output port connected to a lower frequency ESD protection circuit, and wherein the lower frequency ESD protection circuit comprises a lower frequency output. The second stacked coil comprises an output port connected to a higher frequency ESD protection circuit, and wherein the higher frequency ESD protection circuit comprises a higher frequency output.

Abstract: An electrostatic discharge protection circuit includes an electrostatic discharge clamp between a first rail and a second rail, a trigger device configured to activate the electrostatic discharge clamp in response to an electrostatic discharge event, and a charge dissipation element between the first rail and the second rail to dissipate a residual charge at an input of the trigger device.

Abstract: Integrated circuits with enhanced EOS/ESD robustness and methods of designing same. One such integrated circuit includes a plurality of input/output pads, a positive voltage rail, a ground voltage rail, a collection of internal circuits representing the operational core of the integrated circuit, a plurality of input/output buffering circuits connected as inputs and outputs to the internal circuits, wherein the internal circuits and the input/output buffering circuits comprise functional devices, and a plurality of EOS/ESD protection circuits interconnected with the input/output pads to limit ESD voltage and/or shunt ESD current away from the functional devices. At least one of the EOS/ESD protection circuits is a MOSFET. The MOSFET has a source region having an accompanying ohmic contact. The MOSFET further has a rectifying junction contact in place of a drain region and accompanying ohmic contact.

Abstract: An integrated circuit includes a control circuit, a first voltage generation circuit, and a second voltage generation circuit. The control circuit is coupled between a first voltage terminal and a first node, and generates an initiation voltage at the first node. The first voltage generation circuit and the second voltage generation circuit are coupled to a first capacitive unit at the first node and coupled to a second capacitive unit at a second node. The first voltage generation circuit generates, in response to the initiation voltage at the first node, a first control signal based on a first supply voltage to the second voltage generation circuit. The second voltage generation circuit generates, in response to the first control signal received from the first voltage generation circuit, a second control signal to the first node, based on a second supply voltage.

Abstract: Electrical overstress protection of microelectromechanical systems (MEMS) are disclosed herein. In certain embodiments, a MEMS radio frequency system includes a MEMS device electrically connected along a radio frequency signal path that handles a radio frequency signal, and an electrical overstress protection circuit in shunt with the radio frequency signal path and operable to protect the MEMS device from an electrical overstress event, such as an electrostatic discharge (ESD) event received on the radio frequency signal path. The electrical overstress protection circuit includes a metal conductor configured to resonate about at a fundamental frequency of the radio frequency signal.

Abstract: Disclosed is a cascade insert for an ionising bar for the contactless neutralising of electrostatic charges and/or for contactless charging, in particular of insulation materials. The cascade insert includes a housing having at least one cascade circuit which has at least one transformer and a one- or multiple-stage cascade unit, said circuit units being potted with a potting material, and the output of the cascade circuit is coupled capacitively, inductively or resistively with a plurality of electrode points which are accommodated in a carrier extending in the direction of extension of the housing.

Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include electrostatic discharge (ESD) protection circuit structures. The ESD protection circuit structures may be formed in regions other than the region that the IGFETs are formed as well as in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming ESD protection circuit structures in regions below the IGFETs, an older process technology may be used and device size may be decreased. Furthermore, planar IGFETs of FinFETs may be formed in other regions to decrease device size and improve costs.

Abstract: An electrostatic discharge protection circuit, including a discharge switch, a first transistor, an inverter, and a feedback circuit, is provided. The discharge switch is coupled between a first power rail and a second power rail, and may be turned on or cut off according to a control voltage. The first transistor has a first end coupled to the first power rail. A control end of the first transistor receives the control voltage. The inverter is coupled between a second end of the first transistor and a control end of the discharge switch. The feedback circuit is coupled between an output end and an input end of the inverter and is configured to determine whether to provide a turn-on path between the input end of the inverter and the second power rail according to the control voltage.

Abstract: A power conversion circuit having a solid-state circuit breaker integrated therein is disclosed. With a disconnect switch between a utility source and the power conversion apparatus described for meeting UL489, the power conversion circuit includes an input connectable to an AC source, a rectifier circuit connected to the input to convert an AC power input to a DC power, and a DC link coupled to the rectifier circuit to receive the DC power therefrom. The rectifier circuit comprises a plurality of phase legs each including thereon an upper switching unit and a lower switching unit, wherein at least one of the upper and lower switching units on each phase leg comprises a bi-directional switching unit that selectively controls current and withstands voltage in both directions, so as to provide a circuit breaking capability that selectively interrupts current flow through the rectifier circuit, while maintaining original power conversion functionalities.

Abstract: An athletic performance streaming system comprises a sensor system configured to removably attach to an article of clothing worn by an athlete and one or more external devices. The sensor system comprises one or more sensors configured to measure one or more athletic performance parameters for the athlete and a computing unit configured to monitor and transmit the one or more athletic performance parameters. The one or more external devices is remote from the article of clothing. The sensor system is configured to stream the one or more athletic performance parameters in real time to the one or more external devices.

Abstract: A circuit interrupting safety device (CISD) interrupts the flow of current through a pair of lines extending between a source of power and a load. The CISD includes a column reset assembly functioning as a circuit breaker and a contact actuator, a relay circuit including a solenoid, and a fault detecting circuit packaged in a circuit assembly. The solenoid includes a solenoid pin in an extended state when the CISD is reset and a non-extended state when the CISD is tripped.

Abstract: The present disclosure provides an SST driving circuit, a chip, and a driving output method. The SST driving circuit includes: a signal driver for driving and outputting a signal to be driven, the signal driver including termination resistors; a first electrostatic current discharge module, providing first discharge paths for electrostatic currents generated in the signal driver; a second electrostatic current discharge module, connected in series with the termination resistors, providing second discharge paths for the electrostatic currents; and a power clamp, used for conducting the power clamp circuit, the first discharge paths and the second discharge paths when a power supply voltage of the signal driver exceeds a clamping voltage. The present disclosure provides different discharge paths, which effectively reduces voltage borne by a protected device through a voltage division method, and improves the device's ability to protect against electrostatic discharge.

Abstract: The present disclosure provides a power clamp circuit, a chip, and a dual-clamp method. The power clamp circuit is applied to a circuit system to monitor the power supply voltage of the circuit system and includes: an EOS protection module, for outputting an EOS protection triggering signal when it is determined that the circuit system is electrically overstressed based on the power supply voltage; an ESD protection module, for outputting an ESD protection triggering signal when it is determined that an electrostatic event is present in the circuit system based on the power supply voltage; a switch control module, for turning on a discharge path based on the EOS protection signal to discharge an EOS current, and turning on the discharge path based on the ESD protection signal to discharge an electrostatic current.

Abstract: An integrated circuit is provided. An ESD inhibition circuit of the integrated circuit is connected with a first pad, a first node and a second node. The ESD inhibition circuit includes a capacitor bank, a resistor, a voltage selector and a switching transistor. The capacitor bank is connected between the first pad and a third node. The resistor is connected between the third node and the first node. The two input terminals of the voltage selector are connected with the third node and a fourth node, respectively. An output terminal of the voltage selector is connected with a fifth node. A first terminal of the switching transistor is connected with the first pad. A second terminal of the switching transistor is connected with the second node. A gate terminal of the switching transistor is connected with the fifth node.

Abstract: Disclosed is an ESD protection circuit which performs a protection operation by detecting an introduction of an ESD signal when the ESD signal is introduced through a power line. The ESD protection circuit includes a noise detection circuit configured to provide a first detection signal which detects power noise or an ESD signal introduced through a power line; an ESD detection circuit configured to provide a second detection signal which detects an ESD signal introduced through the power line; and a pull-down control circuit configured to perform pull-down on the ESD signal of the power line when the first detection signal which detects the power noise or the ESD signal and the second detection signal which detects the ESD signal are received.

Abstract: A cleaning assembly may include a chuck. The cleaning assembly may include a plurality of lift pins positioned proximate to the chuck. The plurality of lift pins may be configured to engage a cleaning substrate and translate the cleaning substrate to allow the cleaning substrate to capture one or more particles from the surface of the chuck via at least one of electrostatic attraction or mechanical trapping when the cleaning substrate is positioned in the second position. The cleaning assembly may include a replaceable top skin coupled to the chuck and configured to capture the one or more particles.