Patents Examined by Diana J Cheng
  • Patent number: 11909406
    Abstract: An electronic device may include wireless circuitry having mixer circuitry configured to receive an oscillator signal from phase-locked loop circuitry. The phase-locked loop circuitry may include a digital or analog phase-locked loop having a first frequency divider, a ring oscillator, and an auxiliary phase noise cancellation loop coupled to the ring oscillator. The auxiliary phase noise cancellation loop may include at least a time-to-digital converter, a second frequency divider, an amplifier, and a bandpass filter configured to reject thermal and quantization noise associated with the time-to-digital converter. The first frequency divider may have a first division ratio, whereas the second frequency divider may have a second division ratio that is less than the first division ratio to provide faster phase noise correction.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: February 20, 2024
    Assignee: Apple Inc.
    Inventors: Ahmed I Hussein, Mahdi Forghani, David M Signoff
  • Patent number: 11894866
    Abstract: Embodiments presented herein provide apparatus and techniques to reduce a direct current (DC) voltage offset between a transmitter and receiver. Embodiments include a shared reference voltage signal generated by a reference voltage source. The receiver may include a first unit gain buffer to receive a reference voltage signal from the reference voltage source. The transmitter may be communicatively coupled to the receiver via one or more connections and may include a second unit gain buffer communicatively coupled to the first unit gain buffer via one of the connections. An amplifier (e.g., an operation amplifier) of the transmitter may include multiple positive inputs coupled to the second unit gain buffer and an offset tracker. The offset tracker may compensate for a DC offset caused by at least a power supply and/or a ground bounce.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: February 6, 2024
    Assignee: Apple Inc.
    Inventors: Hongrui Wang, Abbas Komijani, Xinhua Chen
  • Patent number: 11876500
    Abstract: A receiver includes a first matching circuit configured to receive antenna input power through a branch point in accordance with a radio signal received by an antenna and input a portion of the received antenna input power to a first circuit as first input power, the antenna input power being input from the antenna, and an impedance of the first matching circuit decreasing as the antenna input power increases, and a second matching circuit configured to receive the antenna input power through the branch point and input another portion of the received antenna input power to a second circuit as second input power, an impedance of the second matching circuit increasing as the antenna input power increases.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: January 16, 2024
    Assignee: FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED
    Inventor: Tetsuya Maruyama
  • Patent number: 11870425
    Abstract: A change rate control circuit computes a first drive speed, which is a gate drive speed of a gate of a drive-subject element, for controlling a change rate of an element voltage of the drive-subject element at a target change rate during a change period. A timing generating circuit acquires, in advance, a delay time caused when the gate is driven and determines a switching timing, at which the element voltage reaches a switching threshold voltage which is lower than a desired switching voltage by a predetermined value, during turn-off of the drive-subject element and generates a timing signal representing the switching timing. A speed change circuit changes the gate drive speed from the first drive speed to a second drive speed at the switching timing during turn-off of the drive-subject element.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: January 9, 2024
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, MIRISE Technologies Corporation
    Inventor: Hironori Akiyama
  • Patent number: 11870449
    Abstract: A clock generator calibration system can include a phased-locked loop and a correction circuit. The PLL can generate an output clock signal, and the correction circuit can adjust a frequency signal of the PLL based on a digital signal of the PLL. The digital signal can be generated based on the adjusted frequency signal.
    Type: Grant
    Filed: December 28, 2019
    Date of Patent: January 9, 2024
    Assignee: Intel Corporation
    Inventors: Elan Banin, Yaniv Cohen, Ofir Degani, Igal Kushnir
  • Patent number: 11870448
    Abstract: In described examples, a phase locked loop (PLL) includes a compensation circuit, a transconductance circuit, and an oscillator. The compensation circuit includes a capacitor circuit and a resistive element having a resistance responsive to a center frequency of the PLL's bandwidth. The transconductance circuit includes a current source and an error amplifier. The current source generates a current responsive to the center frequency. The error amplifier has a transconductance responsive to the center frequency, and receives a signal responsive to the resistance and a difference between an input clock signal and a feedback signal. The oscillator input is coupled to the error amplifier output. The oscillator provides a signal at its output for generating the feedback signal.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: January 9, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Florian Neveu
  • Patent number: 11863172
    Abstract: A single live line switch circuit includes a single live line connecting end, a switch unit, two wire channels, an on-state power obtaining circuit, an off-state power obtaining circuit, and an energy storage element. The single live line connecting end is connected to an external single live line. The on-state power obtaining circuit is connected to the single live line connecting end. The switch unit includes a fixed connecting end and a movable connecting end, and the fixed connecting end is connected to the on-state power obtaining circuit. The two wire channels are provided with a first connecting end and a second connecting end, respectively, and the movable connecting end of the switch unit is in contact with the first connecting end or the second connecting end. A control method of the single live line switch circuit is provided.
    Type: Grant
    Filed: May 31, 2021
    Date of Patent: January 2, 2024
    Assignee: JOULWATT TECHNOLOGY CO., LTD.
    Inventor: Hao Long
  • Patent number: 11848680
    Abstract: This disclosure is directed towards systems and methods that improve bandwidth shifting operations of an ADPLL without losing a lock of the ADPLL and having the benefit of being able to change the bandwidth an unlimited amount of times. Indeed, a processor may transmit amplification parameters to the ADPLL to implement a bandwidth shift. The shift may occur in response to a enable signal, such as a gear trigger control signal (gear_retime signal) or a enable signal generated to cause alignment of the shifting with a clock signal (e.g., enable signal generated by AND logic gates). These systems and methods described herein many enable multiple bandwidth changing operations to occur without compromising the complexity and footprint of the system.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: December 19, 2023
    Assignee: Apple Inc.
    Inventors: Ali Parsa, Ahmed I Hussein
  • Patent number: 11843361
    Abstract: A processor may calibrate a first actuator electrically coupled to a transconductance stage of the frequency conversion circuit. The transconductance stage may be configured to receive a differential signal input. Calibrating a first actuator may adjust a first basis vector associated with a differential direct current (DC) output of the transconductance stage. A processor may calibrate a second actuator electrically coupled to receive the differential current output of the transconductance stage and electrically coupled to a set of commutating devices of the frequency conversion circuit. The commutating devices may be configured to receive differential LO inputs. Calibrating a second actuator may adjust a second basis vector associated with a differential impedance of the set of commutating devices. A processor may offset responsive to adjusting the first basis vector and the second basis vector, the first leakage basis vector and second leakage basis vector of the LO leakage signal.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: December 12, 2023
    Assignee: International Business Machines Corporation
    Inventors: Arun Paidimarri, Bodhisatwa Sadhu, Wooram Lee
  • Patent number: 11843401
    Abstract: A transmitter includes a pre-driver stage circuitry, a post-driver stage circuitry, and resistance adjustment circuits. The pre-driver stage circuitry is configured to output a second data signal according to a first data signal. The post-driver stage circuitry is configured to output a third data signal according to the second data signal. The resistance adjustment circuits are configured to provide a first variable resistor and a second variable resistor, and transmit a first power supply voltage and a second power supply voltage to at least one of the pre-driver stage circuitry or the post-driver stage circuitry, in order to adjust a slew rate of the third data signal.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: December 12, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Chih-Hsun Hsu
  • Patent number: 11838027
    Abstract: An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The TDC is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase difference between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. The normalization circuit selects one of a plurality of candidate gain parameters stored in the normalization circuit in response to the digital output signal, for being utilized as the gain parameter.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: December 5, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventor: Yu-Che Yang
  • Patent number: 11835980
    Abstract: Methods related to controlling switches. In some embodiments, a method for controlling a radio-frequency switch can include providing or generating a control signal to allow generation of a plurality of reference levels by a regulator, or to allow the regulator to be in sleep mode. The method can further include operating the regulator based on the control signal to generate the plurality of reference voltage levels for operation of the radio-frequency switch, or to be in the sleep mode.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: December 5, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: Bang Li Liang, Peter Harris Robert Popplewell, Gregory Edward Babcock
  • Patent number: 11824543
    Abstract: A device includes a first ramp generator having a first ramp generator output configured to provide a first ramp, a second ramp generator having a second ramp generator output configured to provide a second ramp, and a third ramp generator having a third ramp generator output configured to provide a third ramp. The first ramp is a sawtooth voltage waveform having a first common mode voltage and a first peak-to-peak voltage. The second ramp is a sawtooth voltage waveform having a second common mode voltage and a second peak-to-peak voltage. The third ramp is a sawtooth voltage waveform having a third common mode voltage and a third peak-to-peak voltage. A frequency of the second ramp is approximately equal to a frequency of the third ramp, and the frequency of the third ramp is approximately double a frequency of the first ramp.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: November 21, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yinglai Xia, Shailendra Kumar Baranwal, Yogesh Kumar Ramadass, Junmin Jiang
  • Patent number: 11824367
    Abstract: A wireless charging receiving circuit includes a coil, a first energy storage unit, a second energy storage unit, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a filter unit, and a control unit. The coil is connected to the first energy storage unit, the second switch unit and the third switch unit. The first energy storage unit and the first switch unit are connected to the fifth switch unit, and the first switch unit is connected with the filter unit and the fourth switch unit at a first connection node. The fourth switch unit is connected with the second switch unit and the second energy storage unit, and the second energy storage unit is connected with the fifth switch unit, the sixth switch units and the coil.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: November 21, 2023
    Assignee: Halo Microelectronics Co., Ltd.
    Inventors: Shuang Han, Rui Liu, Songnan Yang
  • Patent number: 11817869
    Abstract: A control system for a digitally controlled oscillator with temperature compensation including a loop detector providing an error value, filter circuitry providing a lower resolution digital value to the DCO to generate an output oscillation signal at a frequency within a lower resolution range, tracking circuitry holding a tracking digital value at a tracking offset from center of a tracking range while the lower resolution digital value is being determined, and then regulating the frequency within a higher resolution range by adjusting the tracking digital value, temperature compensation circuitry performing temperature compensation steps to maintain the tracking digital value between first and second thresholds within the predetermined tracking range, and a controller configured to set the first and second thresholds within a narrow range around the tracking offset during a standard operating mode, and to adjust one or both thresholds within a wide range during a critical operating mode.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: November 14, 2023
    Assignee: NXP B.V.
    Inventors: Ulrich Moehlmann, Steffen Rode, Ralf Gero Pilaski
  • Patent number: 11811408
    Abstract: A method includes: selectively generating a first current by a first current generating circuit according to a first control signal; generating a second current by a second current generating circuit; and comparing a first input signal and a second input signal at a common node to generate an output signal according to the first current, the second current, and a second control signal. The second control signal and the first control signal are in-phase with each other.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Mei-Chen Chuang
  • Patent number: 11797035
    Abstract: A voltage regulator includes a slew-up circuit, a slew-down circuit and a transient response control circuit, and provides a regulated output voltage. The slew-up circuit is designed to couple a first node of the voltage regulator to a first constant reference potential upon occurrence of a first condition of the regulated output voltage. The slew-down circuit is designed to couple the first node to a second constant reference potential upon occurrence of a second condition of the regulated output voltage. The transient response control circuit is designed to disable the slew-up circuit and the slew-down circuit upon the rate of change of the regulated output voltage exceeding a predetermined rate. The first node is one of an output node and an output steering node of the voltage regulator. Transient response of the voltage regulator is accordingly improved.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: October 24, 2023
    Assignee: Ningbo Aura Semiconductor Co., Limited
    Inventors: Arnold J D'Souza, Shyam Somayajula
  • Patent number: 11791828
    Abstract: An apparatus comprises a cross-coupled differential amplifier, an inductive-capacitive (LC) tank circuit, and a low-noise voltage supply. The inductive-capacitive (LC) tank circuit is generally coupled in a feedback path of the cross-coupled differential amplifier. The LC tank circuit generally comprises (i) an inductance provided by an inductor, (ii) a first capacitance provided by a parallel coupled varactor circuit, (iii) a second capacitance provided by a parallel coupled first switched-capacitor bank, and (iv) a third capacitance provided by a parallel coupled second switched-capacitor bank. The low-noise voltage supply may be configured to provide a supply voltage of the cross-coupled differential amplifier. The parallel coupled varactor circuit comprises a pair of thick oxide varactors connected with a reverse varactor connection. The parallel coupled first switched-capacitor bank and the parallel coupled second switched-capacitor bank comprise thin oxide switches.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: October 17, 2023
    Assignee: Ambarella International LP
    Inventor: Yueh Chun Cheng
  • Patent number: 11789137
    Abstract: In described examples, a frequency modulated continuous wave (FMCW) synthesizer includes a control engine, and a phase locked loop (PLL) including a frequency divider, a control voltage generator (CVG), and a voltage controlled oscillator (VCO). The frequency divider modifies a VCO output frequency based on a control input. The CVG generates a control voltage based on a frequency reference and the frequency divider output. The VCO outputs a FMCW output having the VCO output frequency in response to the control voltage. The control engine generates the control input so that the VCO output frequency: from a first time to a second time, is a first frequency; from the second time to a third time, changes at a first rate; from the third time to a fourth time, changes at a second rate different from the first rate; and from the fourth time to a fifth time, is a second frequency.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: October 17, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Karthik Subburaj, Sreekiran Samala, Indu Prathapan
  • Patent number: 11777448
    Abstract: A high frequency electromagnetic radiation generation device is disclosed that includes a high voltage input, a nonlinear transmission line, an antenna, and a pulse recirculating circuit. In some embodiments, the high voltage input may be configured to receive electrical pulses having a first peak voltage that is greater than 5 kV, and/or may be electrically coupled with the nonlinear transmission line. The antenna may be electrically coupled with the nonlinear transmission line and/or may radiate electromagnetic radiation at a frequency greater than 100 MHz about a voltage greater than 5 kV. The pulse recirculating may be electrically coupled with the high voltage input and the antenna. The pulse recirculating circuit may include a diode; a low pass filter; and a delay line. In some embodiments, unradiated energy from the antenna is directed through the pulse recirculating circuit to the nonlinear transmission line with a delay of less than 100 ns.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: October 3, 2023
    Assignee: Eagle Harbor Technologies, Inc.
    Inventors: James R. Prager, Timothy M. Ziemba, Kenneth E. Miller