Abstract: An example apparatus includes quantization feedback circuitry (QFC) including an input terminal coupled to an output terminal of voltage-controlled oscillator (VCO) circuitry and an input terminal coupled to an output terminal of first frequency divider circuitry (FDC). The example apparatus also includes second FDC including an output terminal coupled to an input terminal of phase frequency detector (PFD) circuitry and an input terminal coupled to an output terminal of the first FDC. Also, the example apparatus includes masking logic circuitry including an output terminal coupled to an input terminal of the QFC, an input terminal coupled to the output terminal of the VCO circuitry, and an input terminal coupled to the output terminal of the second FDC. The example apparatus also includes adder circuitry including an input terminal coupled to an output terminal of the PFD circuitry and an input terminal coupled to an output terminal of the QFC.

Abstract: Apparatus and methods for radio frequency (RF) switch control are provided. In certain embodiments, a level shifter for an RF switch includes a first level-shifting n-type transistor, a first cascode n-type transistor in series with the first level-shifting n-type transistor between a negative charge pump voltage and a first output that provides a first switch control signal, a first level-shifting p-type transistor, a first cascode p-type transistor in series with the first level-shifting p-type transistor between a positive charge pump voltage and the first output, and a second cascode p-type transistor between a regulated voltage and a gate of the first level-shifting n-type transistor and controlled by a first switch enable signal.

Abstract: In some embodiments, a charge pump system can include a charge pump having a plurality of units driven by respective clock signals having different phases. The plurality of units can provide respective output voltages combined into an output voltage of the charge pump. The charge pump system can further include a feedback circuit configured to compare a scaled value of the output voltage with a reference voltage to generate a comparator output voltage. The charge pump system can further include a level shifter circuit configured to shift the comparator output voltage to a level of the output voltage of the charge pump.

Abstract: Systems and methods are provided for a phase locked loop. A phase/frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase/frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase/frequency detector.

Abstract: A phase-locked loop is disclosed. The phase-locked loop includes a phase error detector, an event detector, a loop filter, and an oscillator. The phase error detector is configured to receive an input signal and a feedback signal and output a phase error signal. The event detector is configured to detect a loss of lock condition based on the phase error signal. The loop filter is configured to filter the phase error signal to generate a filtered control signal based on a first set of filter parameter values, and in response to the loss of lock condition, filter the phase error signal to generate the filtered control signal based on a second set of filter parameter values different from the first set of filter parameter values. The oscillator is configured to output an output signal having a phase that is based on the filtered control signal.

Abstract: A clock generation circuit includes a delay-locked circuit and a duty correction circuit. The delay-locked circuit generates a delay clock signal by delaying an input clock signal and update the delay time of the input clock signal. The duty correction circuit generates a first phase clock signal and a second phase clock signal by delaying the delay clock signal, and updates the delay time of the delay clock signal. The duty correction circuit can prevent or mitigate the delay time of the input clock signal and the delay time of the delay clock signal from being updated simultaneously.

Abstract: A phase locked loop includes a main voltage-controlled oscillator for which an oscillation frequency is adjusted by an offset current and a control voltage (Vctrl), the offset current being set by an offset current setting code (VCO_CON), a phase frequency detector configured to adjust the control voltage by comparing an output signal (mCLK) of the main voltage-controlled oscillator and an input data signal (Data), and an offset current setter configured to generate the offset current setting code for setting the offset current of the main voltage-controlled oscillator. The offset current setter includes n sample voltage-controlled oscillators configured to generate n signals with different frequencies, respectively, and n counters configured to compare frequencies of each of the signals (sCLK) output from the n sample voltage-controlled oscillators and the input data signal, and is configured to generate the offset current setting code based on a comparison result of the n counters.

Abstract: Sidelink (SL) positioning of user equipments (UEs) is supported by providing with SL positioning reference signals (PRS) an indication of the identity of the SL positioning session and the SL PRS source identifier. A UE may transmit a payload-based indication or a sequence-based indication of the identity of the SL positioning session and the source identifier. The pay-load based indication is included in, e.g., a Layer 1 (L1) and/or Layer 2 (L2) control message associated with the SL PRS. The sequence-based indication may be generated using the indication of the identity of the SL positioning session and the source identifier to initialize or seed the generation of the PRS sequence, scramble the PRS sequence, or generate a cover code that is applied to the PRS sequence.

Abstract: This disclosure is directed towards systems and methods that improve bandwidth shifting operations of an ADPLL without losing a lock of the ADPLL and having the benefit of being able to change the bandwidth an unlimited amount of times. Indeed, a processor may transmit amplification parameters to the ADPLL to implement a bandwidth shift. The shift may occur in response to a enable signal, such as a gear trigger control signal (gear_retime signal) or a enable signal generated to cause alignment of the shifting with a clock signal (e.g., enable signal generated by AND logic gates). These systems and methods described herein many enable multiple bandwidth changing operations to occur without compromising the complexity and footprint of the system.

Abstract: A digital clean-up oscillator and associated method are provided for cleaning jitter from a noisy clock signal, comprising receiving a reference clock oscillator signal and the noisy clock signal to be cleaned: measuring the frequency of the reference clock signal in the time domain of the noisy clock signal: filtering any frequency variations from the measured frequency of the reference clock signal on timescales shorter than a phase change interval Tau_clean over which jitter in the noisy clock signal is to be cleaned; generating a phase increment signal DDS_pinc based on the measured and filtered frequency of the reference clock signal: clocking the phase increment signal DDS_pinc with the reference clock signal for generating an output digital phase ramp signal ?_DDS(t) that tracks the frequency of the noisy clock signal with phase wander removed on timescales less than the phase change interval Tau_clean; and converting the output digital phase ramp signal ?_DDS(t) to an output jitter-cleaned time domain

Abstract: An RF switch arrangement includes a shunt switch having a first RF terminal, a second RF terminal coupled to ground, a main control input, and an acceleration control input; a series switch having a first RF terminal coupled to the first RF terminal of the shunt switch, a second RF terminal, a main control input, and an acceleration control input; and a switching time acceleration circuit having a positive acceleration path input, a negative acceleration path input, and a first output coupled to the main control input of the series switch.

Abstract: An electronic device includes a first sample circuit configured to generate a first sampling signal by sampling an input signal in response to edges of a clock signal, a first comparator configured to generate a first logic decision signal by comparing a voltage level of the first sampling signal with a reference voltage level, an analog bang-bang phase detector configured to generate a first detection signal by executing an exclusive OR (XOR) operation on successive samples of the first logic decision signal, and a digitally controlled oscillator configured to vary a frequency of the clock signal according to the first detection signal.

Abstract: Disclosed is a phase-locked loop device. The phase-locked loop device includes a frequency-locked loop circuit and a phase-locked loop circuit. The frequency-locked loop circuit includes a delay generator circuit and a frequency-phase detector. The delay generator circuit generates a ramp signal based on the feedback clock signal, and compares the ramp signal with multiple reference voltages to generate multiple delayed feedback clock signals. The frequency-phase detector has a dead zone control mechanism that generates a locking signal based on phases of the reference clock signal and delayed feedback clock signal and automatically switches on/off the dead zone. The phase-locked loop circuit generates the first output current according to the phase difference between the reference clock signal and the feedback clock signal.

Abstract: Provided are a phase-locked loop frequency synthesizer and control method therefor. The phase-locked loop frequency synthesizer includes: a voltage-controlled oscillator configured to generate a microwave signal; a directional coupler configured to: divide the microwave signal into a primary signal and a coupling signal, and transmit the primary signal into a transmitter of the paramagnetic resonance spectrometer to enter a resonator; an automatic frequency controller connected to the resonator and configured to: generate a first oscillation signal and a second oscillation signal, generate a frequency deviation signal, and generate a frequency setting signal based on the frequency deviation signal; and a phase-locked loop controller connected to the directional coupler, the voltage-controlled oscillator, and the automatic frequency controller and configured to: generate a low-phase-noise signal and control the voltage-controlled oscillator.

Abstract: A phase lock loop (PLL) circuit includes a phase-frequency detector (PFD) circuit that determines a difference between a reference clock signal and a feedback clock signal to generate up/down control signals responsive to that difference. Charge pump and loop filter circuitry generates an integral signal component control signal and a proportional signal component control signal in response to the up/down control signals. The integral signal component control signal and proportional signal component control signal are separate control signals. A voltage controlled oscillator generates an oscillating output signal having a frequency controlled by the integral signal component control signal and the proportional signal component control signal. A divider circuit performs a frequency division on the oscillating output signal to generate the feedback clock signal.

Abstract: A phase-locked loop circuit includes a phase frequency detector (PFD) circuit, a digital code generator circuit, a frequency divider and an oscillator circuit. The PFD circuit is configured to detect a difference in phase and frequency between a reference clock and a feedback clock to generate a first control signal and a second control signal. The digital code generator circuit is configured to process the second control signal to generate a digital code. The frequency divider is configured to receive an output clock to generate the feedback clock. The oscillator circuit is configured to generate the output clock according to the first control signal and the digital code. A frequency of the output clock is determined according to a first control parameter and a second control parameter of different types. The first and second control parameters are adjusted in response to the first control signal and the digital code respectively.

Abstract: An apparatus is disclosed for provision of an indication of an angular difference between first and second input signals. The apparatus comprises a phase frequency detector (PFD) configured to receive the first and second input signals and to provide first and second outputs based on the first and second input signals. A difference in pulse length between signals provided at the first and second outputs is indicative of the phase difference between the first and second input signals. The apparatus also comprises first and second time-to-digital converters (TDCs) each configured to receive one of the signals provided by the PFD and to provide a corresponding digital pulse length representation. Each of the TDCs is a pulse length modifying TDC, wherein pulse length modification may comprise pulse length shrinking or pulse length extension.

Abstract: An apparatus is disclosed for oscillator feedthrough calibration, such as a component arrangement that can be calibrated to account for signal leakage from an oscillator coupled to a mixer circuit. In example aspects, the apparatus includes a mixer circuit having a first stage, a second stage, and tuning circuitry. The first stage includes at least one transistor coupled between a mixer input and a mixer output. The second stage includes one or more transistors coupled between the at least one transistor of the first stage and the mixer output. The one or more transistors are also coupled between a local oscillator signal input and the mixer output. The tuning circuitry includes at least one current source coupled to the at least one transistor of the first stage.

Abstract: Embodiments presented herein provide apparatus and techniques to reduce a direct current (DC) voltage offset between a transmitter and receiver. Embodiments include a shared reference voltage signal generated by a reference voltage source. The receiver may include a first unit gain buffer to receive a reference voltage signal from the reference voltage source. The transmitter may be communicatively coupled to the receiver via one or more connections and may include a second unit gain buffer communicatively coupled to the first unit gain buffer via one of the connections. An amplifier (e.g., an operation amplifier) of the transmitter may include multiple positive inputs coupled to the second unit gain buffer and an offset tracker. The offset tracker may compensate for a DC offset caused by at least a power supply and/or a ground bounce.

Abstract: In an example, a system includes a phase frequency detector (PFD) coupled to a charge pump, and a loop filter coupled to the charge pump. The system also includes a voltage controlled oscillator (VCO) coupled to the loop filter. The system includes a fast Fourier transform (FFT) engine coupled to an output of the VCO, the FFT engine configured to estimate a phase and a magnitude of reference spurs of an input reference signal. The system includes spur correction circuitry coupled to an input of the VCO, the spur correction circuitry configured to correct for the reference spurs of the input reference signal based at least in part on the phase and magnitude of the reference spurs.