Abstract: An apparatus is disclosed for oscillator feedthrough calibration, such as a component arrangement that can be calibrated to account for signal leakage from an oscillator coupled to a mixer circuit. In example aspects, the apparatus includes a mixer circuit having a first stage, a second stage, and tuning circuitry. The first stage includes at least one transistor coupled between a mixer input and a mixer output. The second stage includes one or more transistors coupled between the at least one transistor of the first stage and the mixer output. The one or more transistors are also coupled between a local oscillator signal input and the mixer output. The tuning circuitry includes at least one current source coupled to the at least one transistor of the first stage.

Abstract: Embodiments presented herein provide apparatus and techniques to reduce a direct current (DC) voltage offset between a transmitter and receiver. Embodiments include a shared reference voltage signal generated by a reference voltage source. The receiver may include a first unit gain buffer to receive a reference voltage signal from the reference voltage source. The transmitter may be communicatively coupled to the receiver via one or more connections and may include a second unit gain buffer communicatively coupled to the first unit gain buffer via one of the connections. An amplifier (e.g., an operation amplifier) of the transmitter may include multiple positive inputs coupled to the second unit gain buffer and an offset tracker. The offset tracker may compensate for a DC offset caused by at least a power supply and/or a ground bounce.

Abstract: In an example, a system includes a phase frequency detector (PFD) coupled to a charge pump, and a loop filter coupled to the charge pump. The system also includes a voltage controlled oscillator (VCO) coupled to the loop filter. The system includes a fast Fourier transform (FFT) engine coupled to an output of the VCO, the FFT engine configured to estimate a phase and a magnitude of reference spurs of an input reference signal. The system includes spur correction circuitry coupled to an input of the VCO, the spur correction circuitry configured to correct for the reference spurs of the input reference signal based at least in part on the phase and magnitude of the reference spurs.

Abstract: A switching circuit includes a transmission gate, two base control sub-circuits each including a first transistor and a second transistor, a third transistor, and a fourth transistor. The transmission gate includes two I/O terminals, two gate control terminals, and two base control terminals, and is configured to conduct or not conduct the two I/O terminals according to the voltage of the two gate control terminals. The two base voltage control sub-circuits, the third transistor and the fourth transistor forms a double balance circuit structure and is electrically connected to the transmission gate. The double balance circuit changes the voltage of the base control terminals according to the voltage of the I/O terminals of the transmission gate.

Abstract: The invention relates to a waveguide arrangement for guiding electromagnetic waves, which comprises a rectangular waveguide and a circular waveguide. The rectangular waveguide merges into the circular waveguide at an angle. The circular waveguide is filled with a dielectric which projects into the rectangular waveguide in a transition section. The dielectric filling is beveled at a defined angle in the transition section so that a transition surface is formed by the inner edge at the transition of the waveguide arrangement and the end face of the rectangular waveguide at the transition. The dielectric filling is preferably flush with the closing wall of the rectangular waveguide.

Abstract: A time-to-digital converter (TDC) circuit includes self-referenced delay cell circuits each including: a first inverter coupled with a second inverter, the first inverter receiving a positive time signal representative of an incoming up signal; a third inverter coupled with a fourth inverter, the third inverter receiving a negative time signal representative of an incoming down signal; a first bank of capacitors coupled to a first node between the first/second inverters; and a second bank of capacitors coupled to a second node between the third/fourth inverters. Control logic generates first control signals, each with an up value, to selectively control the first bank of capacitors. Control logic generates second control signals, each with a down value, to selectively control the second bank of capacitors. The up values vary relative to the down values across the first control signals and the second control signals.

Abstract: An antenna system for improved satellite communication with a ground-based terminal device includes a first antenna, a feeding point, and a phase modulation unit. The first antenna is on a surface of a back cover of the terminal device, and the first antenna comprises a plurality of radiation units in an array. The feeding point feeds power and signals to the first antenna. The phase modulation unit can adjust the transmission phase of the different radiation units within the first antenna. The present disclosure also provides a wireless terminal.

Abstract: The present invention provides a quadrature phase detector including a detection circuit. The detection circuit includes a first switch, a second switch and a first filter, wherein the first switch is controlled by a second clock signal to selectively couple a first clock signal to a first node, the second switch is controlled by the second clock signal to selectively coupled the first node to a reference voltage, and the first filter is configured to filter voltages at the first node to generate a first detection result.

Abstract: A circuit device includes: a first phase comparison circuit including a sampling circuit that samples a feedback signal based on a reference clock signal; a first charge pump circuit configured to output a current corresponding to a sampling voltage; a second phase comparison circuit including a dead zone detection circuit that detects whether a phase difference between the reference clock signal and a feedback clock signal falls within a dead zone, and configured to output a phase difference signal when the phase difference does not fall within the dead zone; a second charge pump circuit; and a clock signal generation circuit configured to generate the clock signal having a frequency controlled based on an output of the first charge pump circuit or the second charge pump circuit. The second charge pump circuit is set disabled or in a low power consumption mode in a dead zone period.

Abstract: A technique for assessing positioning qualities within a localization area of a positioning system comprising a plurality of anchor nodes for determining positions of tag devices within the localization area using radio technology is disclosed. A method implementation of the technique comprises determining (S202) a positioning deviation between an absolute position of a tag device and a relative position of the tag device, the absolute position of the tag device being determined by the positioning system using the plurality of anchor nodes and the relative position of the tag device being determined based on movement related measurements performed by the tag device relative to a previously determined absolute position of the tag device, and assessing (S204) a positioning quality for the absolute position based on the determined positioning deviation.

Abstract: A position estimation method for estimating a position of a mobile terminal includes: an acquisition step of acquiring distance values and radio wave intensity values between communication devices provided in a vehicle and the mobile terminal by communicating the communication devices with the mobile terminal; a communication availability determination step of determining that a corresponding communication device is communicable when the distance value is not more than a first value and the intensity value is not less than a second value; an area determination step of, based on a result of the communication availability determination step and communication maps mapping communicable ranges of the communication devices, determining an area where the mobile terminal exists by superimposing the communication maps; and an estimation step of estimating the position of the mobile terminal based on a result of the area determination step.

Abstract: Acoustic resonators, filters, and methods. An acoustic resonator includes a substrate, piezoelectric plate, and a diaphragm comprising a portion of the piezoelectric plate spanning a cavity in a substrate. An interdigital transducer (IDT) on a front surface of the piezoelectric plate includes first and second sets of interleaved interdigital transducer (IDT) fingers extending from first and second busbars respectively. The interleaved IDT fingers are on the diaphragm. Overlapping portions of the interleaved IDT fingers define an aperture of the acoustic resonator. A first dielectric strip overlaps the IDT fingers in a first margin of the aperture and extends into a first gap between the first margin and the first busbar. A second dielectric strip overlaps the IDT fingers in a second margin of the aperture and extends into a second gap between the second margin and the second busbar.

Abstract: The disclosed embodiments provide various compensated charge pumps (CPs) which have a current mismatch compensation circuitry and various CP output-current-mismatch compensation structures based on using a dummy charge pump (CPdum) and feedback loops. In some embodiments, the CPdum is identically biased as the CP to be compensated. CPdum is configured to sense the output voltage and use the feedback loops to generate compensation currents for the CP. The compensation currents simultaneously compensate CP and CPdum. Moreover, CPdum is loaded with high impedance so that the compensation current makes sure CPdum doesn't have current mismatch. Because CP and CPdum have identical biasings and are compensated in the same manner with the same amount of current, CP output current mismatch is hence effectively eliminated.

Abstract: A phase-locked loop or delay locked loop provides a coarse alignment between an input clock and an output clock. A latch receiver circuit provides an indicator of a delay error between the input clock and the output clock. The delay error is used by a control circuit or state machine to adjust a fine delay that affects the output clock signal timing relative to the input clock signal. The fine delay is adjusted to minimize the timing difference between the output clock signal and the input clock signal.

Abstract: A digital phase-locked loop (DPLL) may include a delta-sigma modulator (DSM). The DSM may include a delay component configured to perform noise shaping of a quantization error introduced by the DSM. The DSM may include a noise transfer function (NTF) component configured to perform filtering of the quantization error introduced by the DSM. The DSM may include an adjustment transfer function (ATF) component configured to cause the filtering of the quantization error to be applied on top of the noise shaping such that an impact of the NTF component on the noise shaping is reduced.

Abstract: Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.

Abstract: The present invention belongs to the technical field of 5G millimeter wave communication and discloses a 5G dual-band up-mixer with switching between amplification function and frequency mixing function, and terminal. The first double-balanced active mixer and the second double-balanced active mixer are connected in series, and both ends of the first double-balanced active mixer are connected with a first transformer and a second transformer respectively; both ends of the second double-balanced active mixer are respectively connected with the second transformer and the third transformer; the first double-balanced active mixer is provided with a first MOSFET and a fourth transformer connected with the first MOSFET; the second double-balanced active mixer is provided with a second MOSFET and a fifth transformer connected with the second MOSFET.

Abstract: A transistor is switched on and off with an on-time that is held constant and an off-time that is varied. When the off-time is detected to be less than a threshold value that is greater than a minimum off-time limit, the on-time is extended. Then the power transistor is switched on and off with the extended on-time that is held constant and the off-time that varies.

Abstract: In described examples, a phase locked loop (PLL) includes a compensation circuit, a transconductance circuit, and an oscillator. The compensation circuit includes a capacitor circuit and a resistive element having a resistance responsive to a center frequency of the PLL's bandwidth. The transconductance circuit includes a current source and an error amplifier. The current source generates a current responsive to the center frequency. The error amplifier has a transconductance responsive to the center frequency, and receives a signal responsive to the resistance and a difference between an input clock signal and a feedback signal. The oscillator input is coupled to the error amplifier output. The oscillator provides a signal at its output for generating the feedback signal.

Abstract: Disclosed according to various embodiments are a method for performing a discovery procedure by a first user equipment (UE) in a wireless communication system supporting a sidelink, and an apparatus therefor. Disclosed are a method and an apparatus therefor, the method comprising the steps of: receiving a discovery signal; and transmitting a discovery response signal, wherein the discovery response signal includes information on a first resource region selected from among a plurality of resource regions for sidelink communication related to the discovery signal.