Abstract: High-saturation power Josephson ring modulators and fabrication of the same are provided. A Josephson ring modulator can comprise a plurality of matrix junctions. Matrix junctions of the plurality of matrix junctions can comprise respective superconducting parallel branches that can comprise a plurality of Josephson junctions operatively coupled in a series configuration. A method can comprise forming a first matrix junction comprising arranging a first group of Josephson junctions as first parallel branches. The method can also comprise forming a second matrix junction comprising arranging a second group of Josephson junctions as second parallel branches. Further, the method can comprise forming a third matrix junction comprising arranging a third group of Josephson junctions as third parallel branches. In addition, the method can comprise forming a fourth matrix junction comprising arranging a fourth group of Josephson junctions as fourth parallel branches.

Abstract: Provided is a phase-locked loop circuit, a method for configuring the same, and a communication device. The phase-locked loop circuit includes a phase-locked loop main circuit and a phase temperature compensation circuit. The phase temperature compensation circuit includes at least one phase delay unit connected to the phase-locked loop main circuit and configured to generate a phase shift as a result of a temperature change for cancelling out a phase shift generated by the phase-locked loop main circuit as a result of a temperature change.

Abstract: A system may comprise at least one signal input circuit configured to receive target input signals from at least one sensor device; at least one signal processing unit. Each of the at least one signal processing unit may include at least one signal output circuit configured to output signals to a first electronic connection; and at least one signal extraction circuit configured to obtain a reverse control signal from the first electronic connection; and at least one signal superimposing circuit configured to generate superimposed reverse control signals by superimposing the first reverse control signal with other electronic signals, and output the superimposed reverse control signal to the signal input circuit.

Abstract: A current generating circuit includes a current generator configured to supply a reference current, switches connected to the current generator, wherein one switch of the switches is selected and configured to operate, according to a switch selection signal, and one or more resistors, respectively connected to the switches, wherein a rate of current change according to a temperature change of the current generator is adjusted based on a temperature coefficient of resistance (TCR) of resistors connected to the one switch, according to adjustment of the one switch.

Abstract: A digitally controlled oscillator (DCO) includes; a current mirror configured to generate a supply current in response to a bias voltage matching a reference current, a variable resistor connected to the current mirror through a first node outputting the reference current and configured to provide a variable resistance in response to a first control signal, an oscillation circuit connected to the current mirror through a second node outputting the supply current and configured to generate an oscillation signal in response to the supply current, and a feedback circuit configured to control the bias voltage in relation to at least one of a voltage at the first node and a voltage at the second node.

Abstract: Techniques are disclosed relating to detecting supply voltage events and performing corrective actions. In some embodiments, an apparatus includes sensor circuitry and control circuitry. In some embodiments, the sensor circuitry is configured to monitor supply voltage from a power supply and detect a load release event that includes an increase in the supply voltage that meets one or more pre-determined threshold parameters. In some embodiments, the control circuitry is configured to increase clock cycle time for operations performed by circuitry powered by the supply voltage during a time interval, wherein the time interval corresponds to ringing of the supply voltage that reduces the supply voltage and results from the load release event. In some embodiments, the disclosed techniques may reduce transients in supply voltage (which may avoid equipment damage and computing errors) and may allow for reduced voltage margins (which may reduce overall power consumption).

Abstract: A drive circuit includes a plurality of first control wirings, a plurality of first balance resistors, a first common wiring, a first switch, a plurality of second control wirings, a plurality of second balance resistors, a second common wiring, a second switch, a sensor configured to detect a fault in controlled switches, and a controller configured to control opening and closing of the first switch when the sensor detects no fault, and control opening and closing of the second switch when the sensor detects the fault.

Abstract: The present description concerns a converter comprising: a circuit (C1) supplying a first pulse (P1) determined by an interval between an active edge of a first signal (S1) and an active edge of a second signal (S2); a circuit (INT) which, at each first pulse (P1), integrates the first pulse (P1), a second pulse (P2) starting after the first pulse (P1) in synchronism with a clock signal (clk), and a third pulse (P3) starting after the third pulse (P3) in synchronism with the clock signal (clk); a circuit (C3) sampling over one bit (OUT1) an output signal (RES1) of the integrator circuit (INT) at the beginning of each third pulse (P3); and two circuits (C2, C4) generating, for each first pulse (P1), respectively the corresponding second pulse and the third corresponding pulse based on the first bit (OUT1).

Abstract: In described examples, a charge pump includes an output, first and second transistors, a control circuit, a multiplexer, and a calibration circuit. The first transistor's drain is coupled to the output. The second transistor's drain is part of a current path separate from a current path that includes the first transistor's drain. The control circuit generates a control signal in response to voltages at the gates of the first and second transistors. First and second inputs of the multiplexer are respectively coupled to sources of the first and second transistors. A control input of the multiplexer is coupled to receive the control signal. A first input of the calibration circuit is coupled to an output of the multiplexer. A second input of the calibration circuit receives a reference voltage. First and second outputs of the calibration circuit are respectively coupled to body terminals of the first and second transistors.

Abstract: Enhancing the accuracy in compensating errors caused by a reference signal with unequal successive periods in a fractional-N phase locked loop (PLL). A compensation block generates a compensation factor, and is implemented based on a correction block and a filter. The correction block generates a correction signal containing a first frequency correction factor and a second frequency correction factor for a first period and a second period constituting each pair of successive periods, with the correction signal also containing a noise component at direct current (DC). The filter operates to remove the noise component at DC from the correction signal to generate a compensation factor containing the first frequency correction factor and the second frequency correction factor. The compensation factor thus generated may be provided as an input to a division factor generator of a frequency divider block of the PLL, potentially resulting in zero error frequency synthesis.

Abstract: A tracking system for a digital Phase Locked Loop (PLL), the tracking system including a PLL model configured to emulate an actual internal PLL signal, wherein the emulation is based on another internal PLL signal received from the digital PLL and on an estimated analog PLL parameter of the PLL model; and a tracker configured to compare the emulated internal PLL signal with the actual internal PLL signal, and to update the estimated analog PLL parameter according to a minimization algorithm that minimizes a result of the comparison.

Abstract: An integrated circuit for a power supply circuit that includes a transformer and a transistor controlling an inductor current flowing through a primary winding of the transformer. The integrated circuit includes a terminal receiving a voltage corresponding to the voltage of a secondary winding of the transformer when the transistor is in an off-state, a first detection circuit detecting that the inductor current is smaller than a first current value, and a determination circuit determining whether an AC voltage applied to the primary winding of the transformer is a first or second AC voltage, both based on the received voltage in the off-state of the transistor. The integrated circuit is configured to drive the transistor in response to a detection result of the first detection circuit, a determination result of the determination circuit, and an output voltage of the power supply circuit generated from the AC voltage.

Abstract: An off chip driver circuit includes a first power rail, a second power rail, an input/output pad, a pull-up circuit, a pull-down circuit. The pull-up circuit is configured to selectively activate at least one of charging paths between the first power rail and the input/output pad. The pull-up circuit includes a first resistor and PMOS transistors arranged on the charging paths, and the first resistor is coupled between the first power rail and the PMOS transistors. The pull-down circuit is configured to selectively activate at least one of discharging paths between the second power rail and the input/output pad. The pull-down circuit includes a second resistor and NMOS transistors arranged on the discharging paths, and the second resistor is coupled between the second power rail and the NMOS transistors.

Abstract: The present disclosure relates to a power supply device for a protective relay. The power supply device comprises a power circuit for supplying a power to the control circuit, wherein the power circuit includes: a semiconductor switch element having an input terminal connected to a first node for receiving a direct current, and an output terminal connected to a reference node, wherein the reference node has a voltage lower than a voltage of the first node; and a first voltage drop element disposed between the first node and a second node, wherein the second node is connected to a switching terminal of the semiconductor switch element.

Abstract: A time-to-digital converter (TDC) circuit includes control logic and a first self-referenced delay cell circuit coupled to the control logic. The first self-referenced delay cell circuit includes: a first bank of capacitors coupled to a first node between a first positive input and a first positive output, where the first bank of capacitors is selectively controlled by a first control signal from the control logic, the first control signal including a first up value corresponding to a first positive threshold; and a second bank of capacitors coupled to a second node between a first negative input and a first negative output, where the second bank of capacitors is selectively controlled by a second control signal from the control logic, the second control signal including a first down value corresponding to a first negative threshold.

Abstract: A method of controlling a switch, including: a) applying a control signal to a control terminal of the switch, said control signal exhibiting at least one first switching between a switch turn-on control state and a switch turn-off control state; and b) applying a switch turn-off potential on said control terminal after a first delay starting at said first switching, the first delay being greater than the turn-off time.

Abstract: A contactless PoE connection system and a contactless PoE connector for use in the connection system, in which the contactless PoE connector has a first contactless interface configured for bidirectional data transfer, a second contactless interface configured for unidirectional power transfer, and a third interface to which a first Ethernet line can be connected. The third interface is configured to receive data and power, which are to be transferred jointly via the Ethernet line. Furthermore, a data and power splitting device are connected to the first, second, and third interfaces, which splitting device is configured for splitting power and data as applied to the third interface and for selectively supplying data to the first contactless interface and for selectively supplying power to the second contactless interface.

Abstract: This disclosure describes apparatuses, methods, and techniques for implementing a multimode frequency multiplier. In example implementations, an apparatus for generating a frequency includes a multimode frequency multiplier. The multimode frequency multiplier includes a multiphase generator and a reconfigurable frequency multiplier. The multiphase generator is configured to produce a first signal including multiple phase components and having a first frequency. The reconfigurable frequency multiplier is coupled in series with the multiphase generator. The reconfigurable frequency multiplier is configured to produce a second signal based on the first signal and having a second frequency that is a multiple of the first frequency.

Abstract: A plurality of Phase Locked Loops, PLL (12, 14), are distributed across an Integrated Circuit, each receiving a common reference signal (A). A local phase error (B) of each PLL (12, 14) is connected to a phase error averaging circuit (16), which calculates an average phase error (C), and distributes it back to each PLL (12, 14). In each PLL (12, 14), two loop filters (20, 22) with different bandwidths are deployed. A lower bandwidth, high DC gain, common mode loop operates on the average phase error, and forces the PLL outputs (H) to track the phase of the common reference signal. A high bandwidth, difference mode loop operates on the difference between the local phase error (B) and the average phase error (C) to suppress phase differences between PLL outputs, minimizing interaction between them. The reference noise contribution at the output is controlled by the common mode loop, which can have a low bandwidth.

Abstract: Methods and devices to reduce gate induced drain leakage current in RF switch stacks are disclosed. The described devices utilize multiple discharge paths and/or less negative body bias voltages without compromising non-linear performance and power handling capability of power switches. Moreover, more compact bias voltage generation circuits with smaller footprint can be implemented as part of the disclosed devices.