Abstract: Various embodiments relate to an amplitude shift keying (ASK) demodulator for demodulating an input signal, including: a frequency filter configured to receive the input signal, wherein the frequency filter includes adjustable components configured to adjust the frequency response of the frequency filter; a rectifier configured to rectify an output of the frequency filter, wherein the rectifier includes an adjustable current source configured to adjust the current consumption of the rectifier; a reference signal generator configured to produce a reference signal; a current to voltage converter configured to convert the current of the rectified signal to a rectified voltage and to convert the current of the reference signal to a reference voltage; and a comparator configured to compare the rectified voltage to the reference voltage and to produce a demodulated output signal.

Abstract: The present disclosure discloses a time-to-digital conversion circuit for a clock and data recovery circuit. The time-to-digital conversion circuit may include a first time-to-digital conversion circuit enabled when a phase difference between a clock of an input signal and a recovery clock signal is greater than a reference phase difference and configured to output a first digital signal corresponding to the phase difference, and a second time-to-digital conversion circuit enabled when the phase difference is equal to or smaller than the reference phase difference and configured to output a second digital signal corresponding to the phase difference.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.

Abstract: Disclosed are level shifters and methods of performing level shifting. In one embodiment, a level shifter is disclosed comprising an input, cross-coupled/latch circuitry, a first reference node, a second reference node, and output circuitry coupled between the cross-coupled/latch circuitry and an output, wherein the output circuitry sets the output signal to high based on rising edge of a second reference node and sets the output signal to low based on the rising edge of the first reference node. Further, in some implementations, the first reference node and the second reference node may have signals that are inverse to each other.

Abstract: A system delays input clock signals using time-to-digital converters (TDCs) to convert edges or the clock signals to digital values and storing the digital values in a memory. The digital values are retrieved from the memory based on a desired delay. A time counter used by the TDCs to determine the edges is also used determine the delay. The accuracy and range of the delay depends on the time counter and size of the memory.

Abstract: A circuit for delaying an electric signal (CI), comprises an input for the electric signal (CI); an input for a control signal (EI); a first storage element (U5) for storing the control signal; a delay element for delaying the electric signal; and an output for the delayed electric signal (CO). According to the invention, the electric signal is delayed, based on the stored control signal. The delay circuit is employed in a fast all-digital clock frequency adaptation circuit for voltage droop tolerance.

Abstract: A fractional-N phase locked loop (PLL) and a sliced charge pump (CP) control method thereof are provided. The fractional-N PLL includes a first current source, a first phase frequency detector (PFD), a second current source, a second PFD, and a divided clock controller. The first current source provides a first current. The first PFD generates a first detection signal according to a first divided clock, for controlling the first current source, wherein the first divided clock is generated according to an oscillation clock having an oscillation period. The second current source provides a second current. The second PFD generates a second detection signal according to a second divided clock, for controlling the second current source. The divided clock controller controls the second divided clock based on a variable delay relative to the first divided clock, wherein the variable delay is an integer times the oscillation period.

Abstract: The present disclosure discloses an all-digital phase-locked loop. The all-digital phase-locked loop may include a time-to-digital conversion circuit configured to convert phase differences between a reference signal and a feedback signal into respective digital values and to output a first data signal and a second data signal corresponding to the respective digital values, a digital loop filter configured to select one of the first data signal and the second data signal as valid data and output a control signal by operating the valid data and a first register signal, a digitally controlled oscillator configured to generate an oscillation signal and control a frequency of the oscillation signal in response to the control signal, and a divider configured to divide the oscillation signal and output the feedback signal to the time-to-digital conversion circuit.

Abstract: Embodiments of the invention are directed to a current sensor that includes a current controlled oscillator circuit configured to receive an input current and to provide an output signal having an output frequency which is dependent on the input current. The current sensor further includes a feedforward circuit configured to adapt a reference voltage of the current controlled oscillator in dependence on an instantaneous current value of the input current.

Abstract: The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

Abstract: An analog PLL comprising: a VCO configured to provide a PLL output signal; a phase detector (PD) configured to receive a feedback signal from the VCO and a reference signal and wherein the PD provides a PD signal to a low pass filter (LPF), the LPF configured to filter of the PD signal and provide the filtered signal as a tuning voltage for the VCO; and a tracking loop configured to receive the tuning voltage and comprising at least a tracking loop comparator configured to provide a comparator output voltage based on a difference between the tuning voltage and a target voltage, wherein an output of the tracking loop provides a tracking voltage based on the comparator output voltage and wherein the frequency of the PLL output voltage is based on the tuning voltage and the tracking voltage.

Abstract: A charge pump circuit includes: a charge pump core circuit configured to generate an output voltage, an oscillator configured to provide a clock signal for the charge pump core circuit, and a feedback circuit configured to control the oscillator based on the output voltage, wherein the feedback circuit includes an inner loop.

Abstract: A mixer includes a first unit mixer, a second unit mixer, a third unit mixer, and a fourth unit mixer that have the same configuration and a first combiner, a second combiner, and a third combiner that have the same configuration. The first to the fourth unit mixers each include a differential RF signal terminal. Output of the first unit mixer and output of the second unit mixer are combined by the second combiner. Output of the third unit mixer and output of the fourth unit mixer are combined by the third combiner. Output of the second combiner and output of the third combiner are combined by the first combiner. The output of the third unit mixer is input to the third combiner with the polarity being determined.

Abstract: An apparatus includes a processor, a Phase-Locked Loop Waveform Generator (PLLWG), a Voltage Controlled Oscillator (VCO), a demodulator, signal conditioning circuitry, and an Analog-to-Digital Converter (ADC). The processor generates control command signals, receives a digital data input signal, and performs spectrum analysis on the digital data input signal. The PLLWG is coupled to the processor, receives the control command signals, and generates a charge pump output signal based on the control command signals. The VCO is coupled to the PLLWG, receives a tuning signal based on the charge pump output signal, and outputs a VCO output signal based on the tuning signal. The demodulator receives an incoming modulated signal and the VCO output signal, and outputs an analog output signal based on the incoming modulated signal and the VCO output signal. The ADC converts the analog output signal into the digital data input signal.

Abstract: A clock signal generating circuit includes a detecting circuit configured to generate a first voltage based on first and second clock signals and adjust a level of the first voltage in response to first and second setup voltages and a resistance variable code, a comparing circuit configured to compare the first voltage and a reference voltage and output a check signal according to a comparison result, a code generating circuit configured to perform a first modulation operation for determining the resistance variable code in response to the check signal and perform a second modulation operation for determining a control code in response to the check signal, and an oscillator configured to adjust an amplitude of the first and second clock signals in response to the control code, and output the first and second clock signals having the adjusted amplitude.

Abstract: An integrated circuit includes: a first path suitable for transferring an input signal from a first point to a second point; a second path suitable for transferring the input signal from the second point to a third point; a first phase comparator suitable for comparing an edge of the input signal at the first point with an edge of the input signal at the second point; and a second phase comparator suitable for comparing an edge of the input signal at the second point with an edge of the input signal at the third point, wherein the first path includes a first delay circuit whose delay value is adjusted based on a comparison result of the first phase comparator, and the second path includes a second delay circuit whose delay value is adjusted based on a comparison result of the second phase comparator.

Abstract: A PID loop filter control method and apparatus are provided for generating a control signal to control a digitally controlled oscillator which generates a phase locked loop clock signal, where the PID loop filter includes a proportional-integral-derivative (PID) controller connected and configured to produce a PID controller output signal, and a transformed feedback module having a feedback summer circuit and internal gain stage connected in series to produce an M-bit control signal in response to the PID controller output signal, wherein an output from internal gain stage is provided over a feedback path comprising a feedback gain stage having a configurable Kfb gain value (e.g., 0<Kfb<4) and a filter element to produce the internal feedback signal which is summed with the PID controller output signal to low pass filter high frequency spurs and noise from the PID controller output signal.

Abstract: A PLL circuit includes a fractional-N divider generating a feedback signal, a first phase-frequency detector that compares the feedback signal to a reference signal to generate first up/down control signals that control a charge pump to generate a charge pump output current. A noise cancelation circuit includes a synchronization circuit that generates first and second synchronized feedback signals from the PLL circuit output and the feedback signal, where the first and second synchronized feedback signals are offset by an integer number of cycles of the PLL circuit output. A second phase-frequency detector circuit compares the first and second synchronized feedback clock signals to generate second up/down control signals whose pulse widths differ by the integer number of PLL cycles. A current digital to analog converter circuit is controlled in response to the second up/down control signals to apply noise canceling sourcing and sinking currents to the charge pump output current.

Abstract: In accordance with an embodiment, a method of operating a phase locked loop (PLL), the method including: comparing a phase of a reference signal with a phase of a clock signal using a plurality of parallel matched phase detection circuits to provide a plurality of phase detection signals, where each of the plurality of the parallel matched phase detection circuits is configured to have a same phase difference to output characteristic; filtering a sum of the plurality of phase detection signals to form a filtered phase detection signal; and controlling a frequency of an oscillator using the filtered phase detection signal, where the oscillator is configured to provide the clock signal.

Abstract: Embodiments described herein provide foreign object detection based on coil current sensing. The transmitter power loss is computed directly based on the coil current, in conjunction with, or in place of the conventional computation based on transmitter input current. The enhanced precision of the computer power loss can be used to more accurately detect a foreign object near the transmitter coil during a wireless power transfer.