Abstract: A transistor device includes a transistor cell comprising a channel region, a gate runner that is electrically connected to a gate electrode on the channel region and physically separated from the gate electrode, and a harmonic termination circuit electrically connected to the gate runner between the gate electrode and an input terminal of the transistor device, the harmonic termination circuit configured to terminate signals at a harmonic frequency of a fundamental operating frequency of the transistor device.

Abstract: In an embodiment, a digital output driver circuit comprises an output stage having first and second transistors. A drive stage is configured to drive control terminals of the first and second transistors and comprising switching circuitry and current generator circuitry. In a first configuration, the driver circuit is configured to connect a control terminal of the second transistor to the reference node to turn off the second transistor; and connect a first capacitance to the current generator circuitry and to a control terminal of the first transistor to turn on the first transistor. In a second configuration, the driver circuit is configured to turn off the first transistor and connect the control terminal of the second transistor to the current generator circuitry and to the second capacitance to turn on the second transistor.

Abstract: A convenient electronic circuit in which a switch is able to be switched through electric power obtained using weak radio waves is provided.

Abstract: The present invention relates to a frequency modulation method based on a phase-locked loop capable of performing fast modulation independent of bandwidth. A frequency modulation system based on a phase-locked loop capable of performing fast modulation independent of bandwidth according to the present invention includes a loop filter including a proportional path and an integral path to determine a bandwidth of a phase-locked loop, a voltage-controlled oscillator configured to adjust a frequency according to an output of the loop filter, and a slope alternator configured to alternate an input current of the loop filter, wherein the slope alternator is located in the integral path of the loop filter to generate an offset current at a moment of change from a modulation rise to a modulation fall.

Abstract: Reducing harmonics in a radio transmitter can involve using an electronically tunable harmonic filter (ETHF) in a transmit path at the output of an RF power amplifier stage to reduce harmonic signal components in the RF transmit signal. At least one filter characteristic of the ETHF is selectively controlled using one or more RF switch. The one or more RF switches that are used to control the ETHF can include a CMOS-SOI and/or a MEMs type of switch. Various filter characteristics of the ETHF can be controlled including a bandwidth and/or a center frequency of the ETHF.

Abstract: A semiconductor integrated circuit device includes: first and second transistors provided between a first power source and an output terminal; a step-down circuit that generates a second power source from the first power source; a power source switch circuit that outputs, as a fourth power source, a higher one of potentials of the second power source and a third power source; and a level shifter circuit that transits between the first power source and a fourth power source. The first transistor has a gate connected to an output of the level shifter circuit; the second transistor has a gate connected to the fourth power source.

Abstract: One example charge pump is provided. The example charge pump includes a degeneration circuit, a charging current source transistor, a switch circuit and a discharging current source transistor. The charging current source transistor provides a charging current. The degeneration circuit is coupled between a first terminal of the charging current source transistor and a power supply terminal. The degeneration circuit degrades a first voltage corresponding to the power supply terminal to a second voltage. The switch circuit is coupled between a second terminal of the charging current source transistor and a load. The switch circuit controls a charging current output to the load.

Abstract: An initialization circuit of a delay locked loop (DLL) includes a sense circuit and a control circuit. The sense circuit receives an enable signal, a reference clock signal, and various delayed reference clock signals, and outputs another enable signal. The control circuit receives the two enable signals and outputs and provides a control signal to a loop filter of the DLL to control a delay value associated with the DLL. The control signal is provided to the loop filter such that the delay value associated with the DLL equals a predetermined delay value for a predetermined time duration. Further, after a lapse of the predetermined time duration, the delay value associated with the DLL increases until a difference between a time period of the reference clock signal and the delay value equals a threshold value.

Abstract: An apparatus can implement a frequency doubler with duty cycle correction in conjunction with, for instance, a phase-locked loop (PLL) to decrease phase noise. In an example aspect, an apparatus has a frequency doubler including a signal combiner, a first signal pathway, and a second signal pathway. The frequency doubler also includes a doubler input node and a doubler output node. The signal combiner is coupled to the doubler output node. The first signal pathway is coupled between the doubler input node and the signal combiner and includes a first adjustable delay cell. The second signal pathway is also coupled between the doubler input node and the signal combiner and includes a second adjustable delay cell.

Abstract: A signal generating electric circuit, a signal generating method, a digit-to-time converting electric circuit and a digit-to-time converting method. The signal generating electric circuit includes: a first generating electric circuit configured for, based on a first frequency control word and a reference time unit, generating a periodic first output signal; and a second generating electric circuit configured for, based on a second frequency control word and the reference time unit, generating a periodic second output signal. The first frequency control word includes a first integer part and a first fractional part, the second frequency control word includes a second integer part and a second fractional part, the first integer part is equal to the second integer part, the first fractional part is not zero, the second fractional part is zero, and a period of the first output signal and a period of the second output signal are not equal.

Abstract: The present disclosure discloses a digital loop filter in an all-digital phase-locked loop. The digital loop filter may include a selection circuit configured to output one of a first data signal and a second data signal as valid data, a first operation circuit configured to output a first operation signal by adding or subtracting the valid data and a first register signal, a first register circuit configured to register the first operation signal and output the first operation signal as the first register signal, a second operation circuit configured to output a second operation signal by adding or subtracting a value of at least one bit of the valid data and the first register signal, and a second register circuit configured to store the second operation signal and output the second operation signal as a control signal.

Abstract: The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

Abstract: Examples relate to a digitally controlled oscillator circuit arrangement, a digitally controlled oscillation means, a method for a digitally controlled oscillator, a digital loop filter circuit arrangement, a digital loop filtering means, a method for a digital loop filter, a phase locked loop circuit arrangement and phase locked loop, a user device and a base station.

Abstract: The redundancy control device includes three controllers that output status signals, a majority voting circuit to which a first voltage or a second voltage is supplied as an output signal through an output line of each controller, a switch provided in each output line, a voltage supply unit provided for each output line to supply the second voltage to the output line when the first voltage is lost, a latch circuit provided for each output line to latch the second voltage when the second voltage is supplied thereto and continue to output the second voltage, a comparison circuit provided for each controller to output a comparison signal based on a comparison of the status signals, and a switch control unit provided for each switch to outputs a switch signal to the switch in response to the comparison signal from the comparison circuit.

Abstract: An apparatus is comprised of a processor, a fast-locking Phase-Locked Loop Waveform Generator (PLLWG), an amplifier circuit, and a voltage controlled oscillator (VCO). The processor generates data program signals to program the PLLWG and generates a trigger command signal instructing the PLLWG to generate an analog tuning signal. The PLLWG, coupled to the processor, generates the analog tuning signal based on the trigger command signal. The amplifier circuit, coupled to the PLLWG, receives the analog tuning signal, amplify the analog tuning signal, and generates a control voltage. The VCO, coupled to the amplifier circuit, receives the control voltage and amplifies the control voltage to generate an amplified Radio Frequency (RF) channel frequency signal.

Abstract: A voltage balance circuit including first and second semiconductor devices connected in series with each other is provided with a first transformer having a primary winding and a secondary winding, a second transformer having a primary winding and a secondary winding. A pair of capacitors connected in series with each other and connected between the output terminals of the plurality of semiconductor devices. A first control signal is applied to the control electrode of the first semiconductor device via the primary winding of the first transformer. A second control signal is applied to the control electrode of the second semiconductor device via the primary winding of the second transformer, with one end of each secondary winding connected to each other.

Abstract: Systems and methods are provided for a phase locked loop. A phase/frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase/frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase/frequency detector.

Abstract: Various embodiments relate to an amplitude shift keying (ASK) demodulator for demodulating an input signal, including: a frequency filter configured to receive the input signal, wherein the frequency filter includes adjustable components configured to adjust the frequency response of the frequency filter; a rectifier configured to rectify an output of the frequency filter, wherein the rectifier includes an adjustable current source configured to adjust the current consumption of the rectifier; a reference signal generator configured to produce a reference signal; a current to voltage converter configured to convert the current of the rectified signal to a rectified voltage and to convert the current of the reference signal to a reference voltage; and a comparator configured to compare the rectified voltage to the reference voltage and to produce a demodulated output signal.

Abstract: The present disclosure discloses a time-to-digital conversion circuit for a clock and data recovery circuit. The time-to-digital conversion circuit may include a first time-to-digital conversion circuit enabled when a phase difference between a clock of an input signal and a recovery clock signal is greater than a reference phase difference and configured to output a first digital signal corresponding to the phase difference, and a second time-to-digital conversion circuit enabled when the phase difference is equal to or smaller than the reference phase difference and configured to output a second digital signal corresponding to the phase difference.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.