Directly bonded structures without intervening adhesive and methods for forming the same
A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.
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Any and all applications for which a foreign or domestic priority claim is identified in the Application Data Sheet as filed with the present application are hereby incorporated by reference under 37 CFR 1.57. This application is a continuation of U.S. patent application Ser. No. 16/741,575, filed Jan. 13, 2020, which claims priority to U.S. Patent Application No. 62/792,360, filed Jan. 14, 2019, the entire contents of which are incorporated by reference in their entirety and for all purposes.
BACKGROUND FieldThe field relates to bonded structures and methods for forming the same.
Description of the Related ArtIn various packaging arrangements, it can be advantageous to stack multiple integrated device dies within a low-profile package. For example, three-dimensional (3D) integration techniques often utilize packages in which two or more integrated device dies are stacked on top of and electrically connected to one another. Conventional methods for die thinning and/or 3D integration may have limited product yield because stresses imparted to the dies during assembly may damage dies in the stack, and because it can be challenging to reliably align and connect stacked dies. Accordingly, there remains a continuing need for improved systems and methods for stacking integrated device dies.
These aspects and others will be apparent from the following description of preferred embodiments and the accompanying drawing, which is meant to illustrate and not to limit the invention, wherein:
Various embodiments disclosed herein relate to a bonded structure comprising a first element (e.g., a first integrated device die) having a first side and a second side opposite the first side. The bonded structure can include a second element (e.g., a second integrated device die) having a first side and a second side opposite the first side. The first side of the second integrated device die can be directly bonded to the first side of the first integrated device die without an intervening adhesive along a bonding interface. A protective material can be disposed about a periphery (e.g., respective sidewalls) of the first and second integrated device dies. The protective material can extend from the second side of the first integrated device die to the second side of the second integrated device die. In various embodiments, portions of the protective material can be disposed within gaps between adjacent first integrated device dies or elements. In some embodiments, the protective material can comprise an inorganic dielectric, such as silicon dioxide, silicon nitride, polysilicon, amorphous silicon, etc.
The embodiments disclosed herein can comprise wafer-level processes in which wafers or substrates, serving as carriers, are provided with a plurality of integrated device dies and a protective material (which can comprise one or a plurality of protective layers) over the integrated device dies. The die(s) and protective material can form at least a portion of a reconstituted wafer which can be bonded (e.g., directly bonded without an adhesive) to another reconstituted wafer formed by a similar process. The bonded reconstituted wafers can be singulated to form a plurality of bonded structures, for example after removal of the carriers. The bonded structures can comprise packaging structures in some embodiments. As used herein, direct bond interconnects, or DBI®, can comprise bonded structures in which densely dispersed conductive contacts are bonded to one another without an intervening adhesive. In various embodiments, the surrounding dielectric or nonconductive materials can also be directly bonded without an intervening adhesive. A ZiBond® process can comprise a direct bond between nonconductive materials without an intervening adhesive. Examples of DBI and ZiBond processes and structures may be found throughout at least U.S. Pat. Nos. 9,391,143; 10,141,218; 10,147,641; 9,431,368; and 7,126,212, the entire contents of each of which are incorporated by reference herein in their entireties and for all purposes. Each of the singulated dies mounted on the carriers can be tested prior to mounting, such that all dies in the reconstituted wafer can be Known Good Dies (KGD).
The element 2 can comprise a front side 9 and a back side 10 opposite the front side 9. In various embodiments, the front side 9 can comprise a surface nearest to active circuitry or devices formed in the element 2. A first front bonding layer 4 can be provided at the front side 9 of the element 2. Although the bonding layer 4 is shown at the front side 9 of the element 2, a bonding layer may also or alternatively be provided on the back side 10 for bonding. The bonding layer 4 can comprise one or a plurality of contact pads 6 disposed within or surrounded by a nonconductive field region 5. In some embodiments, the contact pads can comprise copper, although other conductive materials are suitable. In some embodiments, the nonconductive field region can comprise a dielectric such as silicon oxide, silicon nitride, etc. The back side 10 may or may not include active circuitry or devices. In various embodiments, the element 2 can comprise a singulated element (such as a singulated device die) having a side surface 8. The side surface 8 can comprise markings indicative of a singulation process, for example, saw markings, etch patterns, etc.
As explained above, and as shown in
Once the surfaces are prepared, the nonconductive field region 5 of the element 2 can be brought into contact with corresponding nonconductive regions of the carrier 3. The interaction of the activated surfaces can cause the nonconductive region 5 of the element 2 to directly bond with the corresponding nonconductive regions of the carrier 3 without an intervening adhesive, without application of external pressure, without application of voltage, and at room temperature. In various embodiments, the bonding forces of the nonconductive regions can be covalent bonds that are greater than Van der Waals bonds. In some embodiments, only nonconductive field regions of the element 2 are directly bonded to corresponding nonconductive regions of the carrier 3. In other embodiments, however, contact pads 6 of the element 2 can be directly bonded to corresponding conductive contacts of the carrier 3, and the nonconductive region 5 can also be directly bonded to the nonconductive regions of the carrier 3. In such embodiments, direct bonding of the contacts can improve alignment of the element 2 relative to the carrier 3. In the embodiments disclosed herein, the use of direct bonding can reduce movement during assembly as compared to implementations that utilize an intervening adhesive.
As shown in
As shown in
Beneficially, the embodiment of
The protective layer 7 can include one or a plurality of protective layers, including, e.g., inorganic or organic protective layer(s). In the illustrated embodiment, for example, the protective layer 7 can comprise inorganic layer(s) such as silicon oxide, silicon nitride, polysilicon, amorphous silicon, or a metal. In other embodiments, at least a portion of the protective material 7 can comprise an organic material, such as a molding compound or epoxy. In some embodiments, the protective material 7 comprises both a conformal layer and a gap-fill layer. Beneficially, the protective material 7 can assist in affixing the elements 2 to the carrier 3 such that the elements 2 do not shift during subsequent direct bonding processes. The protective material 7 can also assist in protecting the elements 2 during polishing and other processing techniques to prevent damage to the dies (e.g., chipping). Examples of structures and processes for providing protective material 7 on and between adjacent directly bonded dies over a carrier, for use in conjunction with post-bonding thinning and/or singulation processes, are disclosed in U.S. Pat. No. 10,204,893, the entire contents of which are hereby incorporated by reference herein in their entirety and for all purposes.
Turning to
In
In
Additional reconstituted wafers 20a, 20b can be provided as shown in
In the embodiment of
As with
In
In one embodiment, a bonded structure is disclosed. The bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface. The first protective material can be flush with the first bonding surface and the second protective material can be flush with the second bonding surface.
In another embodiment, a bonded structure is disclosed. The bonded structure can include a first reconstituted element comprising a first element and having a first side and a second side opposite the first side. The bonded structure can include a second reconstituted element comprising a second element and having a first side and a second side opposite the first side, the first side of the second reconstituted element directly bonded to the first side of the first reconstituted element without an intervening adhesive along a bonding interface. The bonded structure can include a protective material disposed about respective first and second side surfaces of the first and second elements. The bonded structure can include a nonconductive layer disposed between the first and second elements, the nonconductive layer flush with at least one of the first and second side surfaces of the first and second elements such that an interface is provided between the protective material and the nonconductive layer.
In another embodiment, a bonded structure is disclosed. The bonded structure can include a first reconstituted wafer comprising a plurality of first elements. The bonded structure can comprise a second reconstituted wafer comprising a plurality of second elements. The first and second reconstituted wafers can be directly bonded to one another without an adhesive.
In another embodiment, a bonding method is disclosed. The bonding method can include applying a first protective material over a plurality of first elements to form a first reconstituted wafer. The bonding method can include applying a second protective material over a plurality of second elements to form a second reconstituted wafer. The bonding method can include directly bonding the first reconstituted wafer to the second reconstituted wafer without an adhesive.
In another embodiment, a bonding method is disclosed. The bonding method can include directly bonding a first element to a carrier without an adhesive. The carrier can comprise a silicon carrier with a silicon oxide layer disposed directly onto a surface of the silicon carrier. The silicon oxide layer can be directly bonded to the first element. The silicon oxide layer can comprise a native oxide layer or a thermal oxide layer.
All of these embodiments are intended to be within the scope of this disclosure. These and other embodiments will become readily apparent to those skilled in the art from the following detailed description of the embodiments having reference to the attached figures, the claims not being limited to any particular embodiment(s) disclosed. Although this certain embodiments and examples have been disclosed herein, it will be understood by those skilled in the art that the disclosed implementations extend beyond the specifically disclosed embodiments to other alternative embodiments and/or uses and obvious modifications and equivalents thereof. In addition, while several variations have been shown and described in detail, other modifications will be readily apparent to those of skill in the art based upon this disclosure. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still fall within the scope. It should be understood that various features and aspects of the disclosed embodiments can be combined with, or substituted for, one another in order to form varying modes of the disclosed implementations. Thus, it is intended that the scope of the subject matter herein disclosed should not be limited by the particular disclosed embodiments described above, but should be determined only by a fair reading of the claims that follow.
Claims
1. A bonded structure comprising:
- a substrate including one or more logic or processing devices, the substrate having a first side and a second side opposite the first side, the first side of the substrate having a conductive contact;
- an integrated device die directly hybrid bonded to the first side of the substrate, wherein the integrated device die includes a contact pad electrically connected to the conductive contact of the substrate, wherein the contact pad of the integrated device die is directly bonded to the conductive contact of the substrate without an intervening adhesive, wherein a nonconductive portion of the integrated device die is directly bonded to a nonconductive portion of the first side of the substrate without an intervening adhesive; and
- a dummy element directly bonded to the first side of the substrate.
2. The bonded structure of claim 1, wherein the contact pad comprises copper.
3. The bonded structure of claim 1, wherein the integrated device die comprises a conductive via connecting an active portion of the integrated device die to the contact pad.
4. The bonded structure of claim 1, wherein the dummy element comprises a block of semiconductor material, and the dummy element is directly bonded to the substrate without an intervening adhesive.
5. The bonded structure of claim 4, wherein the semiconductor material comprises silicon.
6. The bonded structure of claim 1, further comprising a second dummy element directly bonded to the first side of the substrate.
7. The bonded structure of claim 6, wherein the integrated device die is disposed between the dummy element and the second dummy element.
8. The bonded structure of claim 1, further comprising a protective material disposed at least partially between the integrated device die and the dummy element.
9. The bonded structure of claim 8, wherein the protective material comprises silicon oxide.
10. The bonded structure of claim 8, wherein the protective material comprises silicon nitride.
11. The bonded structure of claim 8, wherein the protective material fills a gap between the integrated device die and the dummy element.
12. A bonded structure comprising:
- a substrate including one or more logic or processing devices, the substrate having a first side and a second side opposite the first side;
- a first integrated device die directly bonded to the first side of the substrate without an intervening adhesive; and
- first and second electrically inactive elements directly bonded to the first side of the substrate without an intervening adhesive, wherein the first integrated device die is disposed laterally between the first and second electrically inactive elements.
13. The bonded structure of claim 12, wherein the first integrated device die includes a plurality of contact pads directly bonded to a corresponding plurality of conductive contacts of the substrate.
14. The bonded structure of claim 13, wherein the first integrated device die comprises a bonding surface that includes a nonconductive field region and the plurality of contact pads, the nonconductive field region directly bonded to a nonconductive portion of the substrate without an intervening adhesive.
15. The bonded structure of claim 13, wherein the first integrated device die further comprises vias that connect an active portion of the integrated device die and the plurality of contact pads.
16. The bonded structure of claim 12, further comprising a second integrated device die directly bonded to the first side of the substrate without an intervening adhesive.
17. The bonded structure of claim 12, wherein the first and second electrically inactive elements comprise blocks of silicon and a respective bonding layer on the blocks of silicon.
18. A bonding method comprising:
- directly bonding a contact pad of a first integrated device die to a conductive contact on a first side of a substrate without an intervening adhesive, the substrate including one or more logic or processing devices;
- directly bonding a contact pad of a second integrated device die to a conductive contact on the first side of the substrate without an intervening adhesive; and
- directly bonding first and second electrically inactive elements on the first side of the substrate without an intervening adhesive such that the first integrated device die is disposed between the first and second electrically inactive elements.
19. The method of claim 18, wherein providing the first and second electrically inactive elements comprises directly bonding the first and second electrically inactive elements to the substrate without an intervening adhesive.
20. The method of claim 18, further comprising directly bonding a nonconductive portion of the first integrated device die to a nonconductive portion of the first side of the substrate without an intervening adhesive.
21. The method of claim 18, further comprising removing at least a portion of the substrate.
22. The method of claim 21, wherein removing at least a portion of the substrate exposes conductive vias in the substrate.
23. The method of claim 21, further comprising, after removing the at least a portion of the substrate, singulating the substrate into a plurality of bonded structures, each bonded structure having one of the first and second integrated device dies.
24. A method comprising:
- providing a carrier wafer including one or more logic or processing devices, the carrier wafer having a planar upper surface;
- directly bonding lower surfaces of a plurality of singulated dies to the upper surface of the carrier wafer without an intervening adhesive, each of the plurality of singulated dies further comprising side surfaces;
- applying an inorganic protective material along the side surfaces of the plurality of singulated dies and over the upper surface of the carrier wafer to form a reconstituted wafer;
- planarizing an upper surface of the reconstituted wafer;
- forming a bonding layer on the upper surface of the reconstituted wafer; and
- directly bonding a second wafer to the bonding layer of the reconstituted wafer to form a bonded wafer.
25. The method of claim 24, further comprising singulating the bonded wafer into a plurality of bonded structures, wherein at least one of the plurality of bonded structures includes one of the one or more logic or processing devices of the carrier wafer.
26. The method of claim 24, further comprising removing at least a portion of the carrier wafer after directly bonding the second wafer.
27. The method of claim 24, wherein directly bonding lower surfaces of the plurality of singulated dies to the upper surfaces of the carrier wafer comprises directly hybrid bonding at least one singulated integrated device die such that conductive regions on a lower surface of the singulated integrated device die are directly bonded to conductive regions on the upper surface of the carrier wafer and nonconductive regions on the lower surface of the singulated integrated device die are directly bonded to nonconductive regions on the upper surface of the carrier wafer.
28. The method of claim 24, wherein directly bonding lower surfaces of the plurality of singulated dies includes directly bonding an integrated device die and directly bonding dummy dies adjacent to the integrated device die.
29. The method of claim 24, wherein applying an inorganic protective material comprises depositing at least one conformal layer and at least one gap-fill layer.
30. The method of claim 24, wherein the inorganic protective material comprises silicon oxide.
4998665 | March 12, 1991 | Hayashi |
5019673 | May 28, 1991 | Juskey et al. |
5087585 | February 11, 1992 | Hayashi |
5322593 | June 21, 1994 | Hasegawa et al. |
5753536 | May 19, 1998 | Sugiyama et al. |
5771555 | June 30, 1998 | Eda et al. |
5956605 | September 21, 1999 | Akram et al. |
5985739 | November 16, 1999 | Plettner et al. |
5998808 | December 7, 1999 | Matsushita |
6008126 | December 28, 1999 | Leedy |
6080640 | June 27, 2000 | Gardner et al. |
6121688 | September 19, 2000 | Akagawa |
6265775 | July 24, 2001 | Seyyedy |
6374770 | April 23, 2002 | Lee |
6423640 | July 23, 2002 | Lee et al. |
6465892 | October 15, 2002 | Suga |
6582991 | June 24, 2003 | Maeda et al. |
6887769 | May 3, 2005 | Kellar et al. |
6908027 | June 21, 2005 | Tolchinsky et al. |
7045453 | May 16, 2006 | Canaperi et al. |
7078811 | July 18, 2006 | Suga |
7105980 | September 12, 2006 | Abbott et al. |
7126212 | October 24, 2006 | Enquist et al. |
7193423 | March 20, 2007 | Dalton et al. |
7262492 | August 28, 2007 | Pieda et al. |
7354798 | April 8, 2008 | Pogge et al. |
7750488 | July 6, 2010 | Patti et al. |
7781309 | August 24, 2010 | Morita et al. |
7790578 | September 7, 2010 | Furui |
7803693 | September 28, 2010 | Trezza |
7843052 | November 30, 2010 | Yoo et al. |
7932616 | April 26, 2011 | Meguro |
8026181 | September 27, 2011 | Arita et al. |
8178963 | May 15, 2012 | Yang |
8178964 | May 15, 2012 | Yang |
8183127 | May 22, 2012 | Patti et al. |
8241961 | August 14, 2012 | Kim et al. |
8314007 | November 20, 2012 | Vaufredaz |
8349635 | January 8, 2013 | Gan et al. |
8377798 | February 19, 2013 | Peng et al. |
8441131 | May 14, 2013 | Ryan |
8476146 | July 2, 2013 | Chen et al. |
8476165 | July 2, 2013 | Trickett et al. |
8482132 | July 9, 2013 | Yang et al. |
8501537 | August 6, 2013 | Sadaka et al. |
8513088 | August 20, 2013 | Yoshimura et al. |
8524533 | September 3, 2013 | Tong et al. |
8620164 | December 31, 2013 | Heck et al. |
8647987 | February 11, 2014 | Yang et al. |
8697493 | April 15, 2014 | Sadaka |
8716105 | May 6, 2014 | Sadaka et al. |
8802538 | August 12, 2014 | Liu |
8809123 | August 19, 2014 | Liu et al. |
8841002 | September 23, 2014 | Tong |
8975163 | March 10, 2015 | Lei et al. |
8988299 | March 24, 2015 | Kam et al. |
9059010 | June 16, 2015 | Yoshida et al. |
9076860 | July 7, 2015 | Lei et al. |
9076929 | July 7, 2015 | Katsuno et al. |
9093350 | July 28, 2015 | Endo et al. |
9142517 | September 22, 2015 | Liu et al. |
9171756 | October 27, 2015 | Enquist et al. |
9184125 | November 10, 2015 | Enquist et al. |
9224704 | December 29, 2015 | Landru |
9230941 | January 5, 2016 | Chen et al. |
9257399 | February 9, 2016 | Kuang et al. |
9299736 | March 29, 2016 | Chen et al. |
9312229 | April 12, 2016 | Chen et al. |
9331149 | May 3, 2016 | Tong et al. |
9337235 | May 10, 2016 | Chen et al. |
9343433 | May 17, 2016 | Lee et al. |
9355997 | May 31, 2016 | Katkar et al. |
9368866 | June 14, 2016 | Yu |
9385024 | July 5, 2016 | Tong et al. |
9394161 | July 19, 2016 | Cheng et al. |
9437572 | September 6, 2016 | Chen et al. |
9443796 | September 13, 2016 | Chou et al. |
9461007 | October 4, 2016 | Chun et al. |
9466586 | October 11, 2016 | Choi et al. |
9496239 | November 15, 2016 | Edelstein et al. |
9536848 | January 3, 2017 | England et al. |
9559081 | January 31, 2017 | Lai et al. |
9570421 | February 14, 2017 | Wu et al. |
9620481 | April 11, 2017 | Edelstein et al. |
9656852 | May 23, 2017 | Cheng et al. |
9673096 | June 6, 2017 | Hirschler et al. |
9674939 | June 6, 2017 | Scannell |
9722098 | August 1, 2017 | Chung et al. |
9723716 | August 1, 2017 | Meinhold |
9728521 | August 8, 2017 | Tsai et al. |
9741620 | August 22, 2017 | Uzoh et al. |
9799587 | October 24, 2017 | Fujii et al. |
9818729 | November 14, 2017 | Chiu et al. |
9852988 | December 26, 2017 | Enquist et al. |
9865567 | January 9, 2018 | Chaware et al. |
9881882 | January 30, 2018 | Hsu et al. |
9893004 | February 13, 2018 | Yazdani |
9899442 | February 20, 2018 | Katkar |
9929050 | March 27, 2018 | Lin |
9941241 | April 10, 2018 | Edelstein et al. |
9941243 | April 10, 2018 | Kim et al. |
9953941 | April 24, 2018 | Enquist |
9960142 | May 1, 2018 | Chen et al. |
10008844 | June 26, 2018 | Wang et al. |
10026605 | July 17, 2018 | Doub et al. |
10075657 | September 11, 2018 | Fahim et al. |
10204893 | February 12, 2019 | Uzoh et al. |
10269756 | April 23, 2019 | Uzoh |
10276619 | April 30, 2019 | Kao et al. |
10276909 | April 30, 2019 | Huang et al. |
10333623 | June 25, 2019 | Liao et al. |
10410976 | September 10, 2019 | Asano et al. |
10418277 | September 17, 2019 | Cheng et al. |
10446456 | October 15, 2019 | Shen et al. |
10510629 | December 17, 2019 | Chen et al. |
10707087 | July 7, 2020 | Uzoh et al. |
10707145 | July 7, 2020 | Bultitude et al. |
10727204 | July 28, 2020 | Agarwal et al. |
10727219 | July 28, 2020 | Uzoh et al. |
10770430 | September 8, 2020 | Kim et al. |
10790262 | September 29, 2020 | Uzoh et al. |
10840135 | November 17, 2020 | Uzoh |
10854578 | December 1, 2020 | Morein |
10879212 | December 29, 2020 | Uzoh et al. |
10879226 | December 29, 2020 | Uzoh et al. |
10886177 | January 5, 2021 | DeLaCruz et al. |
10892246 | January 12, 2021 | Uzoh |
10923413 | February 16, 2021 | DeLaCruz |
10950547 | March 16, 2021 | Mohammed et al. |
10964664 | March 30, 2021 | Mandalapu et al. |
10985133 | April 20, 2021 | Uzoh |
10991804 | April 27, 2021 | DeLaCruz et al. |
10998292 | May 4, 2021 | Lee et al. |
11011503 | May 18, 2021 | Wang et al. |
11031285 | June 8, 2021 | Katkar et al. |
11056348 | July 6, 2021 | Theil |
11056390 | July 6, 2021 | Uzoh et al. |
11088099 | August 10, 2021 | Katkar et al. |
11127738 | September 21, 2021 | DeLaCruz et al. |
11145626 | October 12, 2021 | Hwang et al. |
11158606 | October 26, 2021 | Gao et al. |
11171117 | November 9, 2021 | Gao et al. |
11176450 | November 16, 2021 | Teig et al. |
11256004 | February 22, 2022 | Haba et al. |
11264357 | March 1, 2022 | DeLaCruz et al. |
11276676 | March 15, 2022 | Enquist et al. |
11329034 | May 10, 2022 | Tao et al. |
11348898 | May 31, 2022 | DeLaCruz et al. |
11355443 | June 7, 2022 | Huang et al. |
20020000328 | January 3, 2002 | Motomura et al. |
20020003307 | January 10, 2002 | Suga |
20020004288 | January 10, 2002 | Nishiyama |
20030148591 | August 7, 2003 | Guo et al. |
20040084414 | May 6, 2004 | Sakai et al. |
20040140546 | July 22, 2004 | Lee et al. |
20040188501 | September 30, 2004 | Tolchinsky et al. |
20040238927 | December 2, 2004 | Miyazawa |
20050040530 | February 24, 2005 | Shi |
20050153522 | July 14, 2005 | Hwang et al. |
20050161808 | July 28, 2005 | Anderson |
20060057945 | March 16, 2006 | Hsu et al. |
20060234473 | October 19, 2006 | Wong et al. |
20070007639 | January 11, 2007 | Fukazawa et al. |
20070096294 | May 3, 2007 | Ikeda et al. |
20070111386 | May 17, 2007 | Kim et al. |
20070123061 | May 31, 2007 | Evertsen et al. |
20070158024 | July 12, 2007 | Addison et al. |
20070222048 | September 27, 2007 | Huang |
20070295456 | December 27, 2007 | Gudeman et al. |
20080036082 | February 14, 2008 | Eun |
20080165521 | July 10, 2008 | Bernstein et al. |
20080265421 | October 30, 2008 | Brunnbauer et al. |
20090029274 | January 29, 2009 | Olson et al. |
20090068831 | March 12, 2009 | Enquist et al. |
20090095399 | April 16, 2009 | Zussy et al. |
20090149023 | June 11, 2009 | Koyanagi |
20090227089 | September 10, 2009 | Plaut et al. |
20090252939 | October 8, 2009 | Park et al. |
20090283898 | November 19, 2009 | Janzen et al. |
20100123268 | May 20, 2010 | Menard |
20110042814 | February 24, 2011 | Okuyama |
20110074033 | March 31, 2011 | Kaltalioglu et al. |
20110186977 | August 4, 2011 | Chi et al. |
20110290552 | December 1, 2011 | Palmateer et al. |
20120025396 | February 2, 2012 | Liao et al. |
20120049344 | March 1, 2012 | Pagaila et al. |
20120077314 | March 29, 2012 | Park et al. |
20120190187 | July 26, 2012 | Yang et al. |
20120212384 | August 23, 2012 | Kam et al. |
20120217644 | August 30, 2012 | Pagaila |
20120238070 | September 20, 2012 | Libbert et al. |
20130037962 | February 14, 2013 | Xue |
20130082399 | April 4, 2013 | Kim et al. |
20130122655 | May 16, 2013 | Yu et al. |
20130169355 | July 4, 2013 | Chen et al. |
20130299997 | November 14, 2013 | Sadaka |
20130334697 | December 19, 2013 | Shin et al. |
20140013606 | January 16, 2014 | Nah et al. |
20140071652 | March 13, 2014 | McShane et al. |
20140154839 | June 5, 2014 | Ahn et al. |
20140175655 | June 26, 2014 | Chen et al. |
20140187040 | July 3, 2014 | Enquist et al. |
20140225795 | August 14, 2014 | Yu |
20140299981 | October 9, 2014 | Goh et al. |
20140312511 | October 23, 2014 | Nakamura |
20140327150 | November 6, 2014 | Jung et al. |
20140370658 | December 18, 2014 | Tong et al. |
20140377909 | December 25, 2014 | Chung et al. |
20150021754 | January 22, 2015 | Lin et al. |
20150048500 | February 19, 2015 | Yu et al. |
20150064498 | March 5, 2015 | Tong |
20150102468 | April 16, 2015 | Kang et al. |
20150113195 | April 23, 2015 | Kim |
20150130082 | May 14, 2015 | Lu et al. |
20150179481 | June 25, 2015 | Lin |
20150206865 | July 23, 2015 | Yu et al. |
20150235949 | August 20, 2015 | Yu et al. |
20150262845 | September 17, 2015 | Hwang et al. |
20150270209 | September 24, 2015 | Woychik et al. |
20150303174 | October 22, 2015 | Yu et al. |
20150340285 | November 26, 2015 | Enquest et al. |
20160035687 | February 4, 2016 | Lin et al. |
20160071770 | March 10, 2016 | Albermann et al. |
20160126634 | May 5, 2016 | Liu et al. |
20160141267 | May 19, 2016 | Hagimoto et al. |
20160190103 | June 30, 2016 | Kabe |
20160233175 | August 11, 2016 | Dubey et al. |
20160300817 | October 13, 2016 | Do et al. |
20160322330 | November 3, 2016 | Lin et al. |
20160343682 | November 24, 2016 | Kawasaki |
20160372323 | December 22, 2016 | Doub et al. |
20170023405 | January 26, 2017 | Fahim et al. |
20170148764 | May 25, 2017 | Wang et al. |
20170194271 | July 6, 2017 | Hsu et al. |
20170200659 | July 13, 2017 | Gaynes et al. |
20170200711 | July 13, 2017 | Uzoh et al. |
20170200756 | July 13, 2017 | Kao et al. |
20170250160 | August 31, 2017 | Wu |
20170250161 | August 31, 2017 | Haba |
20170330855 | November 16, 2017 | Tung |
20170358533 | December 14, 2017 | Briggs et al. |
20170358553 | December 14, 2017 | Kim et al. |
20170365591 | December 21, 2017 | Chang et al. |
20180005992 | January 4, 2018 | Yu et al. |
20180006006 | January 4, 2018 | Kim et al. |
20180012787 | January 11, 2018 | Oka et al. |
20180012863 | January 11, 2018 | Yu et al. |
20180053746 | February 22, 2018 | Yu et al. |
20180068958 | March 8, 2018 | Cho et al. |
20180096931 | April 5, 2018 | Huang et al. |
20180122774 | May 3, 2018 | Huang et al. |
20180130769 | May 10, 2018 | Tan et al. |
20180130772 | May 10, 2018 | Yu et al. |
20180138101 | May 17, 2018 | Yu et al. |
20180158749 | June 7, 2018 | Yu et al. |
20180175012 | June 21, 2018 | Wu et al. |
20180182639 | June 28, 2018 | Uzoh et al. |
20180182666 | June 28, 2018 | Uzoh et al. |
20180190580 | July 5, 2018 | Haba et al. |
20180190583 | July 5, 2018 | DeLaCruz et al. |
20180219038 | August 2, 2018 | Gambino et al. |
20180226375 | August 9, 2018 | Enquist et al. |
20180273377 | September 27, 2018 | Katkar et al. |
20180286805 | October 4, 2018 | Huang |
20180323177 | November 8, 2018 | Yu et al. |
20180323227 | November 8, 2018 | Zhang et al. |
20180331066 | November 15, 2018 | Uzoh et al. |
20180366442 | December 20, 2018 | Gu et al. |
20180366446 | December 20, 2018 | Haba et al. |
20190096741 | March 28, 2019 | Uzoh et al. |
20190096842 | March 28, 2019 | Fountain, Jr. et al. |
20190103409 | April 4, 2019 | Xu et al. |
20190115277 | April 18, 2019 | Yu et al. |
20190123006 | April 25, 2019 | Chen |
20190131277 | May 2, 2019 | Yang et al. |
20190157333 | May 23, 2019 | Tsai |
20190198407 | June 27, 2019 | Huang et al. |
20190198409 | June 27, 2019 | Katkar et al. |
20190265411 | August 29, 2019 | Huang et al. |
20190319007 | October 17, 2019 | Uzoh et al. |
20190333550 | October 31, 2019 | Fisch |
20190333871 | October 31, 2019 | Chen et al. |
20190341306 | November 7, 2019 | Yu et al. |
20190348336 | November 14, 2019 | Katkar et al. |
20190355706 | November 21, 2019 | Enquist et al. |
20190371763 | December 5, 2019 | Agarwal et al. |
20190385935 | December 19, 2019 | Gao et al. |
20190385966 | December 19, 2019 | Gao et al. |
20190385981 | December 19, 2019 | Chen et al. |
20200013637 | January 9, 2020 | Haba |
20200013765 | January 9, 2020 | Fountain, Jr. et al. |
20200035560 | January 30, 2020 | Block |
20200035641 | January 30, 2020 | Fountain, Jr. et al. |
20200075520 | March 5, 2020 | Gao et al. |
20200075534 | March 5, 2020 | Gao et al. |
20200075553 | March 5, 2020 | DeLaCruz et al. |
20200106156 | April 2, 2020 | Lu et al. |
20200118973 | April 16, 2020 | Wang et al. |
20200126906 | April 23, 2020 | Uzoh et al. |
20200176419 | June 4, 2020 | Dabral et al. |
20200194396 | June 18, 2020 | Jzoh |
20200227367 | July 16, 2020 | Haba et al. |
20200243380 | July 30, 2020 | Uzoh et al. |
20200279821 | September 3, 2020 | Haba et al. |
20200294908 | September 17, 2020 | Haba et al. |
20200328162 | October 15, 2020 | Haba et al. |
20200328164 | October 15, 2020 | DeLaCruz et al. |
20200328165 | October 15, 2020 | DeLaCruz et al. |
20200335408 | October 22, 2020 | Gao et al. |
20200371154 | November 26, 2020 | DeLaCruz et al. |
20200395321 | December 17, 2020 | Katkar et al. |
20200411483 | December 31, 2020 | Uzoh et al. |
20210057309 | February 25, 2021 | Hu et al. |
20210098412 | April 1, 2021 | Haba et al. |
20210104487 | April 8, 2021 | Uzoh et al. |
20210118864 | April 22, 2021 | DeLaCruz et al. |
20210143125 | May 13, 2021 | DeLaCruz et al. |
20210181510 | June 17, 2021 | Katkar et al. |
20210183847 | June 17, 2021 | Uzoh et al. |
20210193603 | June 24, 2021 | Katkar et al. |
20210193624 | June 24, 2021 | DeLaCruz et al. |
20210193625 | June 24, 2021 | DeLaCruz et al. |
20210242152 | August 5, 2021 | Fountain, Jr. et al. |
20210296282 | September 23, 2021 | Gao et al. |
20210305202 | September 30, 2021 | Uzoh et al. |
20210366820 | November 25, 2021 | Uzoh |
20210407941 | December 30, 2021 | Haba |
20220020729 | January 20, 2022 | Gao et al. |
20220077063 | March 10, 2022 | Haba |
20220077087 | March 10, 2022 | Haba |
20220139867 | May 5, 2022 | Uzoh |
20220139869 | May 5, 2022 | Gao et al. |
20220189941 | June 16, 2022 | Enquist et al. |
20220208650 | June 30, 2022 | Gao et al. |
20220208702 | June 30, 2022 | Uzoh |
20220208723 | June 30, 2022 | Katkar et al. |
20220246497 | August 4, 2022 | Fountain, Jr. et al. |
20220285303 | September 8, 2022 | Mirkarimi et al. |
20220293567 | September 15, 2022 | Uzoh et al. |
20220319901 | October 6, 2022 | Suwito et al. |
20220320035 | October 6, 2022 | Uzoh et al. |
20220320036 | October 6, 2022 | Gao et al. |
20230005850 | January 5, 2023 | Fountain, Jr. |
20230019869 | January 19, 2023 | Mirkarimi et al. |
20230036441 | February 2, 2023 | Haba et al. |
20230067677 | March 2, 2023 | Lee et al. |
20230069183 | March 2, 2023 | Haba |
103681646 | March 2014 | CN |
107527885 | December 2017 | CN |
2 685 491 | January 2014 | EP |
04-337694 | November 1992 | JP |
2000-100679 | April 2000 | JP |
2001-102479 | April 2001 | JP |
2002-353416 | December 2002 | JP |
2004-193493 | July 2004 | JP |
2009-135348 | June 2009 | JP |
2010-073964 | April 2010 | JP |
2011-171614 | September 2011 | JP |
2013-33786 | February 2013 | JP |
2018-160519 | October 2018 | JP |
10-2001-0104643 | November 2001 | KR |
10-2004-0020827 | March 2004 | KR |
10-2010-0123755 | November 2010 | KR |
10-2015-0097798 | August 2015 | KR |
WO 2005/043584 | May 2005 | WO |
WO 2006/100444 | September 2006 | WO |
WO 2009/005898 | January 2009 | WO |
WO 2010/024678 | March 2010 | WO |
WO 2014/052445 | April 2014 | WO |
WO 2015/134227 | September 2015 | WO |
WO 2017/034654 | March 2017 | WO |
WO 2017/052652 | March 2017 | WO |
WO 2017/151442 | September 2017 | WO |
- Amirfeiz et al., “Formation of silicon structures by plasma-activated wafer bonding,” Journal of The Electrochemical Society, 2000, vol. 147, No. 7, pp. 2693-2698.
- Chung et al., “Room temperature GaAseu + Si and InPeu + Si wafer direct bonding by the surface activate bonding method,” Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, Jan. 2, 1997, vol. 121, Issues 1-4, pp. 203-206.
- Chung et al., “Wafer direct bonding of compound semiconductors and silicon at room temperature by the surface activated bonding method,” Applied Surface Science, Jun. 2, 1997, vols. 117-118, pp. 808-812.
- Farrens et al., “Chemical free room temperature wafer to wafer direct bonding,” J. Electrochem. Soc., The Electrochemical Society, Inc., Nov. 1995, vol. 142, No. 11. pp. 3949-3955.
- Farrens et al., “Chemical free wafer bonding of silicon to glass and sapphire,” Electrochemical Society Proceedings vol. 95-7, 1995, pp. 72-77.
- Frumusanu, Andrei, “TSMC's version of EMIB is ‘LSI’: Currently in pre-qualification,” AnaandTech, https://www.anandtech.com/show/16031/tsmcs-version-of-emib-lsi-3dfabric, Aug. 25, 2020, 6 pages.
- Fukushima, T. et al., “New three-dimensional integration technology using self-assembly technique,” International Electron Devices Meeting Dec. 5-7, 2005, IEEE, Dec. 5, 2005, pp. 348-351.
- Gösele et al., “Semiconductor Wafer Bonding: A flexible approach to materials combinations in microelectronics; micromechanics and optoelectronics,” IEEE, 1997, pp. 23-32.
- Hosoda et al., “Effect of the surface treatment on the room-temperature bonding of Al to Si and SiO2,” Journal of Materials Science, Jan. 1, 1998, vol. 33, Issue 1, pp. 253-258.
- Hosoda et al., “Room temperature GaAs—Si and InP—Si wafer direct bonding by the surface activated bonding method,” Nuclear Inst. and Methods in Physics Research B, 1997, vol. 121, Nos. 1-4, pp. 203-206.
- Howlader et al., “A novel method for bonding of ionic wafers,” Electronics Components and Technology Conference, 2006, IEEE, pp. 7-pp.
- Howlader et al., “Bonding of p—Si/n—InP wafers through surface activated bonding method at room temperature,” Indium Phosphide and Related Materials, 2001, IEEE International Conference on, pp. 272-275.
- Howlader et al., “Characterization of the bonding strength and interface current of p—Si/ n—InP wafers bonded by surface activated bonding method at room temperature,” Journal of Applied Physics, Mar. 1, 2002, vol. 91, No. 5, pp. 3062-3066.
- Howlader et al., “Investigation of the bonding strength and interface current of p—SionGaAs wafers bonded by surface activated bonding at room temperature,” J. Vac. Sci. Technol. B 19, Nov./Dec. 2001, pp. 2114-2118.
- International Search Report and Written Opinion dated Sep. 22, 2017, issued in International Application No. PCT/US2017/029187, 20 pages.
- International Search Report and Written Opinion dated Apr. 22, 2019 in International Application No. PCT/US2018/064982, 13 pages.
- International Search Report and Written Opinion dated May 7, 2020, issued in International Application No. PCT/US2020/013377, 16 pages.
- Itoh et al., “Characteristics of fritting contacts utilized for micromachined wafer probe cards,” 2000 American Institute of Physics, AIP Review of Scientific Instruments, vol. 71, 2000, pp. 2224.
- Itoh et al., “Characteristics of low force contact process for MEMS probe cards,” Sensors and Actuators A: Physical, Apr. 1, 2002, vols. 97-98, pp. 462-467.
- Itoh et al., “Development of MEMS IC probe card utilizing fritting contact,” Initiatives of Precision Engineering at the Beginning of a Millennium: 10th International Conference on Precision Engineering (ICPE) Jul. 18-20, 2001, Yokohama, Japan, 2002, Book Part 1, pp. 314-318.
- Itoh et al., “Room temperature vacuum sealing using surface activated bonding method,” The 12th International Conference on Solid State Sensors, Actuators and Microsystems, Boston, Jun. 8-12, 2003, 2003 IEEE, pp. 1828-1831.
- Ker, Ming-Dou et al., “Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS Ics,” IEEE Transactions on Components and Packaging Technologies, Jun. 2002, vol. 25, No. 2, pp. 309-316.
- Kim et al., “Low temperature direct Cu—Cu bonding with low energy ion activation method,” Electronic Materials and Packaging, 2001, IEEE, pp. 193-195.
- Kim et al., “Room temperature Cu—Cu direct bonding using surface activated bonding method,” J. Vac. Sci. Technol., 2003 American Vacuum Society, Mar./Apr. 2003, vol. 21, No. 2, pp. 449-453.
- Kim et al., “Wafer-scale activated bonding of Cu—CU, Cu—Si, and Cu—SiO2 at low temperature,” Proceedings—Electrochemical Society, 2003, vol. 19, pp. 239-247.
- Matsuzawa et al., “Room-temperature interconnection of electroplated Au microbump by means of surface activated bonding method,” Electornic Components and Technology Confererence, 2001, 51st Proceedings, IEEE, pp. 384-387.
- Moriceau, H. et al., “Overview of recent direct wafer bonding advances and applications,” Advances in Natural Sciences—Nanoscience and Nanotechnology, 2010, 11 pages.
- Nakanishi, H. et al., “Studies on SiO2—SiO2 bonding with hydrofluoric acid. Room temperature and low stress bonding technique for MEMS,” Sensors and Actuators, 2000, vol. 79, pp. 237-244.
- Oberhammer, J. et al., “Sealing of adhesive bonded devices on wafer level,” Sensors and Actuators A, 2004, vol. 110, No. 1-3, pp. 407-412, see pp. 407-412, and Figures 1(a)-1 (I), 6 pages.
- Onodera et al., “The effect of prebonding heat treatment on the separability of Au wire from Ag-plated Cu alloy substrate,” Electronics Packaging Manufacturing, IEEE Transactions, Jan. 2002, vol. 25, Issue 1, pp. 5-12.
- Plobi, A. et al., “Wafer direct bonding: tailoring adhesion between brittle materials,” Materials Science and Engineering Review Journal, 1999, R25, 88 pages.
- Reiche et al., “The effect of a plasma pretreatment on the Si/Si bonding behaviouir,” Electrochemical Society Proceedings, 1998, vol. 97-36, pp. 437-444.
- Roberds et al., “Low temperature , in situ, plasma activated wafer bonding,” Electrochecmical Society Proceedings, 1997, vol. 97-36, pp. 598-606.
- Shigetou et al., “Room temperature bonding of ultra-fine pitch and low-profiled Cu electrodes for bump-less interconnect,” 2003 Electronic Components and Technology Conference, pp. 848-852.
- Shigetou et al., “Room-temperature direct bonding of CMP—Cu film for bumpless interconnection,” Electronic Components and Technology Confererence, 51st Proceedings, 2001, IEEE, pp. 755-760.
- Shingo et al., “Design and fabrication of an electrostatically actuated MEMS probe card,” Transducers, Solid-State Sensors, Actuators and Microsystems, 12th International Conference, Jun. 8-12, 2003, vol. 2, pp. 1522-1525.
- Suga et al., “A new approach to Cu—Cu direct bump bonding,” IEMT/IMC Symposium, 1997, Joint International Electronic Manufacturing Symposium and the International Microelectronics Conference, Apr. 16-18, 1997, IEEE, pp. 146-151.
- Suga et al., “A new bumping process using lead-free solder paste,” Electronics Packaging Manufacturing, IEEE Transactions on (vol. 25, Issue 4), IEEE, Oct. 2002, pp. 253-256.
- Suga et al., “A new wafer-bonder of ultra-high precision using surface activated bonding (SAB) concept,” Electronic Components and Technology Conference, 2001, IEEE, pp. 1013-1018.
- Suga et al., “Bump-less interconnect for next generation system packaging,” Electronic Components and Technology Conference, 2001, IEEE, pp. 1003-1008.
- Suga, T., “Feasibility of surface activated bonding for ultra-fine pitch interconnection—A new concept of bump-less direct bonding for system level packaging,” The University of Tokyo, Research Center for Science and Technology, 2000 Electronic Components and Technology Conference, 2000 IEEE, pp. 702-705.
- Suga, T., “Room-temperature bonding on metals and ceramics,” Proceedings of the Second International Symposium on Semiconductor Wafer Bonding: Science, Technology and Applications, The Electrochemical Society Proceedings, vol. 93-29 (1993), pp. 71-80.
- Suga et al., “Surface activated bonding—an approach to joining at room temperature,” Ceramic Transactions: Structural Ceramics Joining II, The American Ceramic Society, 1993, pp. 323-331.
- Suga et al., “Surface activated bonding for new flip chip and bumpless interconnect systems,” Electronic Components and Technology Conference, 2002, IEEE, pp. 105-111.
- Suga, “UHV room temperature joining by the surface activated bonding method,” Advances in science and technology, Techna, Faenza, Italie, 1999, pp. C1079-C1089.
- Takagi et al., “Effect of surface roughness on room-temperature wafer bonding by Ar beam surface activation,” Japanese Journal of Applied Physics, 1998, vol. 37, Part 1, No. 1, pp. 4197.
- Takagi et al., “Low temperature direct bonding of silicon and silicon dioxide by the surface activation method,” Solid State Sensors and Actuators, 1997, Transducers '97 Chicago, 1997 International Conference, vol. 1, pp. 657-660.
- Takagi et al., “Room-temperature bonding of lithium niobate and silicon wafers by argon-beam surface activation,” Appl. Phys. Lett., 1999. vol. 74, pp. 2387.
- Takagi et al., “Room temperature silicon wafer direct bonding in vacuum by Ar beam irradiation,” Micro Electro Mehcanical Systems, MEMS '97 Proceedings, 1997, IEEE, pp. 191-196.
- Takagi et al., “Room-temperature wafer bonding of Si to LiNbO3, LiTaO3 and Gd3Ga5O12 by Ar-beam surface activation,” Journal of Micromechanics and Microengineering, 2001, vol. 11, No. 4, pp. 348.
- Takagi et al., “Room-temperature wafer bonding of silicon and lithium niobate by means of arbon-beam surface activation,” Integrated Ferroelectrics: An International Journal, 2002, vol. 50, Issue 1, pp. 53-59.
- Takagi et al., “Surface activated bonding silicon wafers at room temperature,” Appl. Phys. Lett. 68, 2222 (1996).
- Takagi et al., “Wafer-scale room-temperature bonding between silicon and ceramic wafers by means of argon-beam surface activation,” Micro Electro Mechanical Systems, 2001, MEMS 2001, The 14th IEEE International Conference, Jan. 25, 2001, IEEE, pp. 60-63.
- Takagi et al., “Wafer-scale spontaneous bonding of silicon wafers by argon-beam surface activation at room temperature,” Sensors and Actuators A: Physical, Jun. 15, 2003, vol. 105, Issue 1, pp. 98-102.
- Tong et al., “Low temperature wafer direct bonding,” Journal of Microelectomechanical systems, Mar. 1994, vol. 3, No. 1, pp. 29-35.
- Topol et al., “Enabling technologies for wafer-level bonding of 3D MEMS and integrated circuit structures,” 2004 Electronics Components and Technology Conference, 2004 IEEE, pp. 931-938.
- Uhrmann, T. et al., “Heterogeneous integration by collective die-to-wafer bonding,” Chip Scale Review, Nov./Dec. 2018, vol. 22, No. 6, pp. 10-12.
- Wang et al., “Reliability and microstructure of Au—Al and Au—Cu direct bonding fabricated by the Surface Activated Bonding,” Electronic Components and Technology Conference, 2002, IEEE, pp. 915-919.
- Wang et al., “Reliability of Au bump—Cu direct interconnections fabricated by means of surface activated bonding method,” Microelectronics Reliability, May 2003, vol. 43, Issue 5, pp. 751-756.
- “Die-to-Wafer Fusion and Hybrid Bonding,” EV Group, https://www.evgroup.com/technologies/die-to-wafer-fusion-and-hybrid-bonding/, printed Sep. 21, 2022, 8 pages.
- Gao, G. et al., “Low temperature hybrid bonding for die to wafer stacking applications,” 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), IEEE, Jun. 1, 2021-Jul. 4, 2021.
- Hooper, A. et al. “Review of wafer dicing techniques for via-middle process 3DI/TSV ultrathin silicon device wafers,” 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).
- “Lecture 29: Productivity and process yield,” National Programme on Technology Enhanced Learning (NPTEL), MM5017: Electronic materials, devices, and fabrication, 16 pages.
- “The effects of edge trimming—Engineering R&D Division, Operation V,” Disco Technical Review Mar. 2016, 3 pages.
- Chang, T.C. et al., “A method for fabricating a superior oxide/nitride/oxide gate stack,” Electrochemical and Solid-State Letters, 2004, vol. 7, No. 7, pp. G138-G140.
- Jin, H. et al., “Silicon / Silicon Oxide / LPCVD Silicon Nitride Stacks: The Effect of Oxide Thickness on Bulk Damage and Surface Passivation,” Centre for Sustainable Energy Systems, Faculty of Engineering and Information Technology, The Australian National University, Canberra ACT 0200, Australia, 3 pages.
- Weldon et al., “Physics and chemistry of silicon wafer bonding investigated by infrared absorption spectroscopy,” Journal of Vacuum Science & Technology B, Jul./Aug. 1996, vol. 14, No. 4, pp. 3095-3106.
- Xu et al., “New Au—Al interconnect technology and its reliability by surface activated bonding,” Electronic Packaging Technology Proceedings, Oct. 28-30, 2003, Shanghai, China, pp. 479-483.
- Ceramic Microstructures: Control at the Atomic Level, Recent Progress in Surface Activated Bonding, 1998, pp. 385-389.
Type: Grant
Filed: Dec 28, 2021
Date of Patent: Nov 14, 2023
Patent Publication Number: 20220199560
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC. (San Jose, CA)
Inventors: Belgacem Haba (Saratoga, CA), Rajesh Katkar (Milpitas, CA), Ilyas Mohammed (Santa Clara, CA), Javier A. DeLaCruz (San Jose, CA)
Primary Examiner: Didarul A Mazumder
Application Number: 17/563,506
International Classification: H01L 23/00 (20060101); H01L 21/78 (20060101);