Abstract: A system-in-package module with memory includes a non-memory chip, a substrate, and a memory chip. The non-memory chip has a first portion and a second portion. The substrate has a window and the substrate is electrically connected to the second portion of the non-memory chip. The memory chip is placed into the window of the substrate to electrically connect the first portion of the non-memory chip, and there is no direct metal connection between the memory chip and the substrate.

Abstract: An internal buffer caches data from a memory. A memory address conversion unit receives as input a read request from a request source. A hit determination unit determines whether or not data of any one of two or more read out candidate addresses in which payload data requested by the read request and corresponding are stored has been cached or is going to be cached in the internal buffer. When data of any one of the addresses has been cached or is going to be cached in the internal buffer, a command issue interval control unit outputs to the memory a partial read command to instruct to read data from an address other than the address of the data that has been cached or is going to be cached in the internal buffer out of the read out candidate addresses, after a predetermined delay time has elapsed.

Abstract: In one embodiment, a method includes reading packets of data from M parallel data tracks of a magnetic tape to obtain a plurality of (D+P)-symbol codewords which are logically arranged in nM encoded blocks, each packet including a row of an encoded block, where each encoded block includes an array having rows and columns of code symbols, wherein symbols of each of the (D+P)-symbol codewords are distributed over corresponding rows of the nM encoded blocks, decoding sub-blocks from rows and columns of a plurality of product codewords from the nM encoded blocks, each product codeword including a logical array of code symbols having the rows which include respective row codewords and the columns which include respective column codewords, where each sub-block includes a logical array having rows and columns of data symbols, combining the sub-blocks to form a block of data, and outputting the block of data.

Abstract: Aspects of the invention relate to test access architecture for stacked memory and logic dies. A test access interface for a logic die that is stacked under a memory die is disclosed. The disclosed test access interface can control testing logic core, interconnections with the memory die and with another logic die. The controlling of testing interconnections with the memory die is through a memory boundary scan register controller in the test access interface.

Abstract: A method begins by a dispersed storage (DS) processing module segmenting a data partition into a plurality of data segments. For a data segment of the plurality of data segments, the method continues with the DS processing module dividing the data segment into a set of data sub-segments and generating a set of sub keys for the set of data sub-segments based on a master key. The method continues with the DS processing module encrypting the set of data sub-segments using the set of sub keys to produce a set of encrypted data sub-segments and aggregating the set of encrypted data sub-segments into encrypted data. The method continues with the DS processing module generating a masked key based on the encrypted data and the master key and combining the encrypted data and the masked key to produce an encrypted data segment.

Abstract: The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.

Abstract: A system and method for calculating a bit error rate for a mask is described. For each time during the time duration of the mask, the minimum and maximum voltages of the mask at that time are determined. The maximum bit error rate can be calculated for each time by integrating between those voltages. The maximum bit error rate for all times during the time duration of the mask can be selected as the maximum bit error rate for the mask.

Abstract: A radiation upset detector is provided. The radiation upset detector includes at least one radiation sensitive memory initialized with at least one respective known-signature word; and at least one radiation hardened logic circuitry communicatively coupled to the at radiation sensitive memory to check the known-signature word at at least a kHz rate to detects errors. Responsive to detecting an error in the known-signature word in the radiation sensitive memory, the radiation hardened logic circuitry sends an action command. At least one of: a memory size of the memory; a number of circuits in the logic circuitry; a clock rate for the checking the known-signature word; and at least one corruption threshold is selected based on system reliability requirements of the protected system including at least one of: an overall operational reliability requirement of the protected system; a probability of detection success; false alarm rates; and a required speed of detection.

Abstract: Disclosed is a method for providing error correction to a video stream transmitted from a server to a client device, wherein the server is connected to an intermediate module over a bandwidth-limited network and the intermediate module is connected to the client device over a lossy network. The method includes intercepting data transmitted from the bandwidth-limited network to the lossy network by the intermediate module, identifying the video stream for error correction from the intercepted data at the intermediate module, generating error correction data for the video stream by the intermediate module and transmitting a modified stream that includes the video stream and the error correction data over the lossy network to the client device by the intermediate module.

Abstract: A method and an apparatus for transmitting and receiving a packet in a broadcasting and communication system are provided. The method and apparatus allows a receiver to recognize data in a packet lost due to data loss occurring in a network. To this end, Forward Error Correction (FEC) control-related information is generated, a packet including the generated FEC control-related information is generated, and the packet is transmitted. The FEC control-related information includes at least one of FEC configuration-related information and FEC encoding configuration-related information.

Abstract: A post package repair (PPR) device is disclosed, which relates to a technology for masking a rupture operation in case of a post package repair (PPR) operation. The post package repair (PPR) device includes: a plurality of bank groups, each including a fuse indicating repair information, configured to share a predetermined number of fuses; a resource detection unit configured to generate a resource signal which determines whether the fuses from among the plurality of bank groups are available; and a masking controller configured to output a masking signal which prevents repeated execution of a rupture operation when there is no unused fuse in response to the resource signal and a bank active signal.

Abstract: Systems and methods are described for reading a storage element of a memory. In a particular embodiment, a method, in a data storage device including a controller and a non-volatile memory, where the non-volatile memory includes a plurality of storage elements, includes performing multiple read operations at a storage element of the non-volatile memory. Each read operation of the multiple read operations is performed using the same reading voltage. The method further includes determining a read value of the storage element based on the multiple read operations.

Abstract: A packet transmission method is provided herein. The packet transmission method is adapted for a wireless distribution system. The packet transmission method includes: generating a packet by an access controller or a wireless access point; determining whether the packet belongs to CAPWAP (Control and Provisioning of Wireless access point s) packet; adding a tag into a packet descriptor corresponding to the packet when the packet belongs to CAPWAP packet; transmitting the packet to the wireless access point or transmitting the packet to the access controller; determining whether an error is occurred during transmitting the packet; determining whether the packet descriptor corresponding to the packet includes the tag when the error is occurred during transmitting the packet; and adding the packet into a queue when the packet descriptor corresponding to the packet includes the tag.

Abstract: An integrated circuit (IC) that is operable in scan test and functional modes includes scan-in pads, scan-out pads, scan chains, a compressor, a decompressor, a test control register, and a scan controller. The scan controller includes a multiple input shift register (MISR), an inverter, and multiple logic gates. The scan-in and scan-out pads receive scan test data and masking signals, respectively. The decompressor provides decompressed scan test data to the scan chains, which generate functional responses based on the decompressed scan test data. The compressor provides compressed functional responses to the scan controller. The logic gates receive the compressed functional responses and the masking signals from the compressor and the corresponding scan-out pads, respectively, and generate corresponding masked signals. The masking signals mask non-deterministic values in the decompressed functional responses. The MISR receives the masked signals and generates an error free signature.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

Abstract: Integrated circuits with single event upset (SEU) detection circuitry are provided. The SEU detection circuitry may include an error detection block for detecting soft errors and a sensitivity processor that determines whether or not to correct the detected soft errors. The sensitivity processor may be used to access a sensitivity map header (SMH) file that is stored on external memory. The sensitivity map header file contains information that can help identify which logic region on the integrated circuit the soft error affects and whether or not that soft error can critically cause functional failure for the integrated circuit. Depending on the criticality of the soft error, different corrective actions may be taken.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

Abstract: Apparatus and method for managing a media cache through the monitoring of operational vibration of a data storage device. In some embodiments, a non-volatile media cache of the data storage device is partitioned into at least first and second zones having different data recording characteristics. Input data are received for storage in a non-volatile main memory of the data storage device. An amount of operational vibration associated with the data storage device is measured. The input data are stored in a selected one of the first or second zones of the media cache prior to transfer to the main memory responsive to a comparison of the measured amount of operational vibration to a predetermined operational vibration threshold.

Abstract: A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.