Abstract: A method begins with a set of storage units of a dispersed storage network (DSN) receiving a plurality of read requests for encoded data slices corresponding to particular content data. The method continues with a first storage unit detecting that a corresponding portion of the plurality of read requests exceeds a heavy load condition for the first storage unit. The method continues when the corresponding portion of the plurality of read requests exceeds the heavy load condition for the first storage unit with the first storage unit identifying a first alternative storage unit of the DSN. The method continues with the first storage unit sending a copy of the first group of encoded data slices to the first alternative storage unit and redirecting some of the corresponding portion of the plurality of read requests to the first alternative storage unit for processing.

Abstract: An integrated circuit may have a memory bit corruption detection circuit. The memory bit corruption detection circuit may monitor a circuit that stores multiple data bits using a current sensing circuit and a fault detection circuit. When a bit of the data bits gets corrupted, a current may flow through a predetermined node in the monitored circuit which may be sensed by the current sensing circuit. The current may have a particular current profile that may be distinguishable from current flows that occur during normal operation of the monitored circuit. The fault detection circuit may recognize the particular current profile that is indicative of a corrupted memory bit in the monitored circuit and generate a fault signal to indicate that memory bit corruption has occurred in the monitored circuit.

Abstract: An apparatus having mapping and interface circuits. The mapping circuit (i) generates a coded item by mapping write unit bits using a modulation or recursion of past-seen bits, and (ii) calculates a particular state to program into a nonvolatile memory cell. The interface circuit programs the cell at the particular state. Two normal cell states are treated as at least four refined states. The particular state is one of the refined states. A mapping to the refined states mitigates programming write misplacement that shifts an analog voltage of the cell from the particular state to an erroneous state. The erroneous state corresponds to a readily observable illegal or atypical write sequence, and results in a modified soft decision from that calculated based on the normal states only. A voltage swing between the particular state and the erroneous state is less than between the normal states.

Abstract: A 4B5B encoder converts an inputted 4-bit data into a pattern of a 5-bit data in which (i) the number of bits of consecutive “0” data values is permitted to be maximum two, and, simultaneously, (ii) maximum one bit of head end two bits is permitted to have a “0” data value and maximum one bit of tail end two bits is permitted to have a “0” data value. A 5N-bit command encoder converts a command into a command pattern in which the number of bits contained in consecutive “0” data values is permitted to be maximum two. The data after the conversion and the command after the conversion are converted into NRZI codes by an NRZI encoder.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

Abstract: Non-volatile memory block management. A method according to one embodiment includes determining a block health of at least some non-volatile memory blocks of a plurality of non-volatile memory blocks that are configured to store data. An error count margin threshold is calculated for each of the at least some non-volatile memory blocks. A determination is made as to whether the error count margin threshold of any of the at least some non-volatile memory blocks has been exceeded. A memory block management function is triggered upon determining that the error count margin threshold of any of the non-volatile memory blocks has been exceeded.

Abstract: A memory device has a controller, an address integrity feature, and an address register. The controller is configured to store error correction data in the address register when the address integrity feature is enabled.

Abstract: A semiconductor memory apparatus includes a first comparison block configured to compare a plurality of channel data with one another and generate a first comparison signal, or output one of the plurality of channel data as the first comparison signal, in response to a plurality of channel select signals; a second comparison block configured to compare the plurality of channel data and generate a second comparison signal when the plurality of channel select signals have a predetermined combination and a channel detection signal has a predetermined logic level; a channel selection detection block configured to enable the channel detection signal when only one channel select signal among the plurality of channel select signals is enabled; and a combined output block configured to enable a test result signal when at least one comparison signal of the first and second comparison signals is enabled.

Abstract: According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge.

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain includes at least a first segment and a second segment. A first portion of a test pattern is scanned into the first segment by clocking a first scan cell of the first segment with an even clock while clocking a remainder of the plurality of scan cells in the first segment with an odd clock, in which the odd clock is out of phase with the even clock, in which the even clock and odd clock have a rate equal to a scan rate of the test pattern divided by an integer N. A second portion of the test pattern is scanned into the second segment by clocking the plurality of scan cells in the second segment with the odd clock, such that the second portion of the test pattern is not scanned into the first segment.

Abstract: A semiconductor device includes a latch circuit suitable for storing a test result; a non-volatile memory circuit suitable for storing information used for an operation of the semiconductor device; a decoding unit suitable for generating one or more internal program commands by using one or more control signals; and a control unit suitable for programming information in the non-volatile memory circuit in response to the test result stored in the latch circuit when the internal program commands are activated.

Abstract: A distributed heterogeneous or homogeneous file storage system divides logical responsibility for data from actual control of the data by using separate file and storage managers. Each file manager provides access to stored files and stores metadata associated with each of the files for which it is responsible. A file manager control component allocates responsibilities among file managers, assigns management responsibilities for individual files, and maintains a record of which files are assigned to each manager. Each storage manager is responsible for managing storage of files on data storage devices and maintains a record of the location of each stored file. A storage manager control component allocates responsibilities among storage managers, assigns responsibilities for individual files, and maintains a record of which files and storage devices are assigned to each manager.

Abstract: A method includes storing a first subset of encoded data slices of a set of encoded data slices in one local memory, LAN memory, and/or WAN memory. The method further includes storing a second subset of encoded data slices in a different one of the local memory, the LAN memory, and the WAN memory. The method further includes determining to make a change in storage of the set of encoded data slices. The method further includes determining to make an adjustment to the pillar width number based on the determined storage change. The method further includes generating adjusted encoded data slices for the set of encoded data slices based on the adjustment to the pillar width number. The method further includes storing the updated set of encoded data slices in accordance with the determined change in the storage of the set of encoded data slices.

Abstract: Technologies are generally described herein to detect unidirectional resistance drift errors in a multilevel cell of a phase change memory. The resistance levels of the multilevel cell of the phase change memory may be encoded to detect unidirectional resistance drift errors. In some examples, Berger Code-compatible encoding may be used. When a word is written to the multilevel cell, a write check code may be generated. The write check code may be a binary representation of the number of zeroes contained in the word as written. When the word is read from the multilevel cell, a read check code may be generated. The read check code may be a binary representation of the number of zeroes contained in the word as read. An error can be detected if a comparison indicates that the write check code and the read check code are different.

Abstract: Various aspects described or referenced herein are directed to different methods, systems, and computer program products for implementing hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: Systems and methods are provided for using a product code having a first dimension and a second dimension to encode data, decode data, or both. An encoding method includes receiving a portion of user data to be written in the first dimension, and computing first parity symbols with respect to the first dimension for the portion of user data. Partial parity symbols with respect to the second dimension are computed for the portion of user data and are used to obtain second parity symbols for the portion of user data. A decoding method includes decoding a first codeword in the first dimension. When the decoding the first codeword in the first dimension is successful, a target syndrome of a second codeword in the second dimension is computed based on a result of the decoding of the first codeword, wherein the first codeword partially overlaps with the second codeword.

Abstract: A method of reading from a memory module which includes a plurality of memories is provided. The method includes reading data corresponding to a plurality of burst length units from the plurality of memories; correcting an error of the read data using a storage error correction code; and outputting the error corrected data by a unit of data corresponding to one burst length unit.

Abstract: A method includes storing, by non-local DSN memory, redundancy encoded data slices of a set of encoded data slices. The method includes storing, by each DS processing module, a copy of the decode threshold number of encoded data slices in local memory. The method includes receiving, by the plurality of DS processing modules, read requests for the set of encoded data slices from user devices. The method includes, in response to a read request, determining, by a DS processing module, that at least one encoded data slice is unavailable; retrieving, by the DS processing module, at least one of the redundancy encoded data slices from the non-local DSN memory; and processing, by the DS processing module, the read request based on the retrieved at least one of the redundancy encoded data slice and available encoded data slices of the local copy of the decode threshold number of encoded data slices.