Abstract: A semiconductor chip includes an input pad and an output pad formed on the semiconductor chip; at least one bump formed on the semiconductor chip; and a test scan chain configured to output data applied from the input pad, to a node which is electrically coupled with the bump, store data corresponding to capacitance of the node by floating the node for a predetermined time, and output data corresponding to the stored capacitance, to the output pad.

Abstract: A processor generates a parity from dummy data attached to a first piece of data of a plurality of pieces of data and a piece of data other than the first piece of data when writing the plurality of pieces of data into a first storage apparatus. Then, the processor stores the parity in a second storage apparatus. The processor performs a reading-out process in parallel with a restoration process when reading out the plurality of pieces of data from the first storage apparatus and writing them into the second storage apparatus. The reading-out process is a process to read out the first piece of data from the first storage apparatus and to write it into the second storage apparatus, and the restoration process is a process to restore a second piece of data among the plurality of pieces of data by using the dummy data and the parity.

Abstract: Devices implement encapsulation to support link layer preemption. The device may include a encapsulation logic that encapsulates data, such as an Ethernet frame, to produce an encapsulated frame. The encapsulated frame may include an encapsulation element that indicates whether the encapsulated data includes non-preemptible data, such as Distinguished Minimum Latency Traffic (DMLT), or preemptible data. The encapsulated frame may also indicate whether the encapsulated data comprises the last fragment of a preemptible frame.

Abstract: A memory system includes a memory module that supports error detection and correction (EDC) in a manner that relieves a memory controller or processor of some or all of the computational burden associated with EDC. Individual EDC components perform EDC functions on subsets of the data, and share data between themselves using relatively short, fast interconnections.

Abstract: In one embodiment, a first set of digital data (e.g., an image) is tested for the presence of a certain feature (e.g., a certain face), yielding one of two outcomes (e.g., not-present, or present). If the testing yields the first outcome, no additional testing is performed. If, however, the testing yields the second outcome, further testing is performed to further check this outcome. Such further testing is performed on a second set of digital data that is based on, but different from, the first set of data. Only if the original testing and the further testing both yield the same second outcome is it treated as a valid result. A variety of other features and arrangements are also detailed.

Abstract: The patent application discloses mechanisms that, for a given channel step or edge response, bit interval, and data dependent jitter table can directly determine the minimal eye or bit error rate opening by building a worst case pattern considering the effect of data dependent jitter. These mechanisms can be based on building an indexed table of jitter samples, preparing a structure in the form of connected elements corresponding to the jitter samples, and then applying dynamic programming to determine paths through the connected elements.

Abstract: A method for operating a data storage device that includes reading data and storage parity data, generating transformation parity data through a masking operation on the storage parity data, and performing an error correcting operation on the data, based on the transformation parity data.

Abstract: A data decoding apparatus includes a first decision unit suitable for determining whether or not an error is present in a read data based on a first decoding method and identifying an error occurrence position, wherein the read data is read by a first read voltage, a second decision unit suitable for determining a low reliability position that belongs to the error occurrence position by checking reliability of the error occurrence position based on a second read voltage changed from the first read voltage within a set range, and an error correction unit suitable for generating an error correction data by correcting an error of the low reliability position.

Abstract: An integrated circuit device such as a programmable integrated circuit may include interface circuits and associated identification circuits. The identification circuits may be coupled to shared mixer circuitry that performs a logic function on mixer input signals received from the identification circuits of that integrated circuit to produce a mixer output signal. Debug computing equipment may be used to test integrated circuits having mixer circuitry. The debug computing equipment may have interfaces that receive connections to interface circuits of the integrated circuits. The debug computing equipment may communicate with the mixer circuitry of the integrated circuits through each of the connected interface circuits to identify groups of interfaces that are connected to different devices. For each device, the debug computing equipment may select an interface from the corresponding group of interfaces and perform test debug operations over the selected interface.

Abstract: An operating method of a data storage device includes performing an error correcting operation for first data and verifying the error correcting operation to determine whether one or more error decision bits determined as an error through the error correcting operation are actual error bits or normal bits, when a result of the error correcting operation is a pre-correction success.

Abstract: A semiconductor memory device includes; a memory cell array comprising a first sub-memory cell array storing first data having a first characteristic and a second sub-memory cell array storing second data having a second characteristic different from the first characteristic, a first peripheral circuit operatively associated with only the first sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the first sub-memory cell array, and a second peripheral circuit operatively associated with only the second sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the second sub-memory cell array.

Abstract: Systems and methods are provided for generating a likelihood value. A detector identifies a winning path through a trellis and a plurality of losing paths through the trellis and computes path metric differences within the trellis based on the winning path and at least some of the plurality of losing paths. The detector calculates a pair of error metrics based on the path metric differences and determines the likelihood value based on a difference between the pair of error metrics.

Abstract: Methods and apparatuses are provided for transmitting and receiving in a communication system. Input information is encoded by using a first parity check matrix to generate a codeword. Additional parity bits are generated by using a second parity check matrix which is related with the first parity check matrix. The codeword is transmitted by using a first resource. The additional parity bits are transmitted by using a second resource which is different from the first resource.

Abstract: A frame generation method in an optical transmission system that transmits a transmission frame including a payload area for storing therein information data and an FEC redundant area for storing therein an error correcting code with respect to the information data is provided, in which coding gain is calculated based on the quality of a communication path through which the transmission frame is transmitted, and, when it is determined that redundancy is insufficient with an error correcting code stored in the FEC redundant area based on the coding gain, a variable parity area for storing therein the error correcting code is set in the payload area and a transmission frame in which the error correcting code is stored in the FEC redundant area and the variable parity area is generated.

Abstract: A data alignment method is provided by iteratively increasing the delay of each data input line of a system component until a test signal transmitted on each data input line is received at the system component at substantially a predetermined time.

Abstract: There are provided a method and apparatus for decoding an LDPC code. In this specification, a first result is calculated by performing the calculation of a check node having two inputs forward and recursively, a second result is calculated by performing the calculation of the check node having the two inputs backward and recursively, and the check node is calculated using the first result and the second result as the inputs.

Abstract: Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. Other embodiments including additional apparatuses and methods are described.

Abstract: Methods are systems for calculating log-likelihood ratios for a decoder utilized in an electronic non-volatile computer storage apparatus are disclosed. A log-likelihood ratio handler is configured to provide an input log-likelihood ratio to the decoder, wherein the input log-likelihood ratio is one of: a uniform input log-likelihood ratio for all bits calculated based on an estimated raw bit error rate for a particular data unit, or a bit-based input log-likelihood ratio for each bit calculated based on a confidence value for a cell containing said each bit. The decoder of the electronic non-volatile computer storage apparatus is configured to decode encoded data at least partially based on the input log-likelihood ratio from the log-likelihood ratio handler.

Abstract: An apparatus and method for acquiring data of fast fail memory includes a pattern generator for generating a pattern to be recorded to a device under test (DUT) and receiving DUT data from the DUT; a data transmitter for sending the DUT data and the pattern generated so as to correspond thereto to a failure analyzer from the pattern generator; and a failure analyzer for analyzing the DUT data and the pattern generated so as to correspond to the DUT data, which are received from the data transmitter, thus producing failure analysis information. The data transmitter (FIFO) able to advance the failure analysis time allows failure analysis to be performed before completion of testing, thereby shortening the total failure analysis time and overcoming hardware limitations for failure analysis.

Abstract: A method of data encoding is disclosed. An encoder receives a set of information bits and performs an LDPC encoding operation on the set of information bits to produce a codeword based on a matched lifted LDPC code. The matched lifted LDPC code is based on a commutative lifting group and includes a number of parity bits and a submatrix to determine values of the parity bits. An order of the lifting group (Z) corresponds with a size of the lifting. A determinant of the submatrix is a polynomial of the form: ga+(g0+gL)P, where g0 is the identity element of the group, g0=gL2k, and P is an arbitrary non-zero element of a binary group ring associated to the lifting group.