Patents Examined by Dmitriy Yemelyanov
  • Patent number: 11227932
    Abstract: Aspects of the disclosure provide a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11217674
    Abstract: A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: January 4, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Yuki Nakano
  • Patent number: 11217705
    Abstract: A semiconductor element capable of adjusting a barrier height ?Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the “change of the barrier height caused by the bias” described above up to a deep degeneration range. An electron Fermi level (EF) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: January 4, 2022
    Assignee: NTT ELECTRONICS CORPORATION
    Inventors: Makoto Shimizu, Hiroki Itoh, Tadao Ishibashi, Isamu Kotaka
  • Patent number: 11195782
    Abstract: Reliability of a semiconductor device is improved. In the semiconductor device SA1, a snubber capacitor pad SNP electrically connected to the capacitor electrode of the snubber capacitor is formed on the surface of the semiconductor chip CHP.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: December 7, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoki Fujita, Hiroyuki Nakamura
  • Patent number: 11189627
    Abstract: In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a pad stack over a semiconductor substrate, where the pad stack includes a lower pad layer and an upper pad layer. An isolation structure having a pair of isolation segments separated in a first direction by the pad stack is formed in the semiconductor substrate. The upper pad is removed to form an opening, where the isolation segments respectively have opposing sidewalls in the opening that slant at a first angle. A first etch is performed that partially removes the lower pad layer and isolation segments in the opening so the opposing sidewalls slant at a second angle greater than the first angle. A second etch is performed to round the opposing sidewalls and remove the lower pad layer from the opening. A floating gate is formed in the opening.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ling Shih, Chieh-Fei Chiu, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Yong-Shiuan Tsair, Shih Kuang Yang
  • Patent number: 11171194
    Abstract: A display apparatus is provided. The display apparatus includes a display substrate and a plurality of pads arranged above the display substrate. Each of the plurality of pads includes a first conductive layer, at least a portion of which is covered by an insulating film, a second conductive layer arranged above the first conductive layer, and a clamping portion formed in the second conductive layer.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: November 9, 2021
    Inventors: Seungsoo Ryu, Byoungyong Kim, Sanghyeon Song, Jeongdo Yang, Jungyun Jo, Seunghwa Ha, Jeongho Hwang
  • Patent number: 11164779
    Abstract: Semiconductor devices including bamboo tall via interconnect structures and methods of forming the bamboo tall via interconnect structures generally include a first via in a first dielectric layer including a liner layer and a bulk conductor in the first via, wherein the bulk conductor includes a recess filled with a conductive metal different from the bulk conductor and selected to prevent diffusion of the bulk conductor. At least one additional via is in a second dielectric layer including a liner layer and a bulk conductor in the least one additional via, wherein the second dielectric layer is on the first dielectric layer, and wherein the bulk conductor includes a recess filled with a conductive metal different from the bulk conductor and selected to prevent diffusion of the bulk conductor. The at least one additional via is aligned with the first via.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: November 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Michael Rizzolo, Theodorus E. Standaert
  • Patent number: 11152379
    Abstract: A Static Random-Access Memory (SRAM) device and its manufacturing method are presented, relating to semiconductor techniques. The SRAM device includes: a substrate; a first semiconductor column for Pull-Up (PU) transistors and a second semiconductor column for Pull-Down (PD) transistors, with both the first and the second semiconductor columns on the substrate; a first separation region, and a gate stack structure. The first separation region is between the first and the second semiconductor columns and comprises a first region and a second region, the gate stack structure comprises a gate dielectric layer comprising a first part and a second part; a P-type work function regulation layer comprising a first area and a second area adjacent to each other; a N-type work function regulation layer comprising a third area and a fourth area adjacent to each other; and a gate on both the P-type and N-type work function regulation layers.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: October 19, 2021
    Inventor: Yong Li
  • Patent number: 11152417
    Abstract: The present disclosure is directed to anchor structures and methods for forming anchor structures such that planarization and wafer bonding can be uniform. Anchor structures can include anchor layers formed on a dielectric layer surface and anchor pads formed in the anchor layer and on the dielectric layer surface. The anchor layer material can be selected such that the planarization selectivity of the anchor layer, anchor pads, and the interconnection material can be substantially the same as one another. Anchor pads can provide uniform density of structures that have the same or similar material.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu Wei, Cheng-Yuan Li, Hsin-Chi Chen, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
  • Patent number: 11152256
    Abstract: A carrier film according to an embodiment of the present invention comprises: a base film; and a first adhesive layer formed on a surface of the base film such that an element to be transferred is attached to the first adhesive layer, wherein the magnitude of force of adhesion between the element and the first adhesive layer is in proportion to the depth of press-fitting at which the element is press-fitted into the first adhesive layer.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: October 19, 2021
    Assignees: KOREA INSTITUTE OF MACHINERY & MATERIALS, CENTER FOR ADVANCED META-MATERIALS
    Inventors: Yun Hwangbo, Byung-Ik Choi, Jae-Hyun Kim, Hak Joo Lee, Bongkyun Jang, Yeon Woo Jeong, Seong Min Hong
  • Patent number: 11148946
    Abstract: A structure including a first layer of one or more molecular components having a first top anchor group, a first functional moiety and a first bottom anchor group. The first functional moiety connects the first top anchor group to the first bottom anchor group. The structure further includes a first conductive film of one or more nanoparticles disposed on the first layer of one or more molecular components. Each of at least a portion of the one or more nanoparticles bond with the first top anchor group of the one or more molecular components. Each of at least a portion of the one or more nanoparticles cross-link with at least one other of the nanoparticles. The first conductive film forms a first contact for the first layer of one or more molecular components.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Emanuel Loertscher, Marcel Mayor, Gabriel Fernando Puebla Hellman
  • Patent number: 11152545
    Abstract: Devices and techniques are disclosed herein which include a die including side surfaces such that light emitted from the die can exit through the side surfaces. The die includes a first surface and a second surface opposite the first surface such that the distance between the first surface and the second surface is at least 100 micro meters. The die also include a wavelength converting material deposited external to the die such that the wavelength converting material covers the side surfaces. The wavelength converting material includes phosphor particles, a transparent risen carrier, and transparent particles configured to increase the volume of the wavelength converting material, the transparent particles having a refractive index (RI) that is similar to the RI of the transparent risen carrier.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: October 19, 2021
    Assignee: Lumileds LLC
    Inventors: Rene Helbing, Daniel Estrada, Kentaro Shimizu
  • Patent number: 11152451
    Abstract: A display panel and a display device are provided. The display panel includes a substrate, a plurality of signal lines, a plurality of fan-out lines, and a resistance balance member. The substrate defines a display area and a fan-out area. The signal lines are defined in the display area, and the fan-out lines are defined in the fan-out area and are electrically communicated with the signal lines. The fan-out area defines a central winding line region and a peripheral straight line region. The resistance balance member is connected to one fan-out line of the peripheral straight line region in series.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: October 19, 2021
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yu-Jen Chen
  • Patent number: 11145667
    Abstract: In a memory device, a lower memory cell string is formed over a substrate to include a first channel structure, a plurality of first word line layers and first insulating layers. The first channel structure protrudes from the substrate and passes through the first word line layers and first insulating layers. An inter deck contact is formed over the lower memory cell string and connected with the first channel structure. An upper memory cell string is formed over the inter deck contact. The upper memory cell string includes a second channel structure, a plurality of second word lines and second insulating layers. The second channel structure passes through the second word lines and second insulating layers, and extends to the inter deck contact, and further extends laterally into the second insulating layers. A channel dielectric region of the second channel structure is above the inter deck contact.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: October 12, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Ruo Fang Zhang, Enbo Wang, Haohao Yang, Qianbing Xu, Yushi Hu, Fushan Zhang
  • Patent number: 11139198
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 5, 2021
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Lu Fei, Jeffrey L. Libbert, Andrew M. Jones, Alex Usenko, Gang Wang, Shawn George Thomas, Srikanth Kommu
  • Patent number: 11114559
    Abstract: A semiconductor device includes a first group of trench-like structures and a second group of trench-like structures. Each trench-like structure in the first group includes a gate electrode contacted to gate metal and a source electrode contacted to source metal. Each of the trench-like structures in the second group is disabled. The second group of disabled trench-like structures is interleaved with the first group of trench-like structures.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: September 7, 2021
    Assignee: Vishay-Siliconix, LLC
    Inventors: Chanho Park, Kyle Terrill
  • Patent number: 11094591
    Abstract: Semiconductor structures and fabrication methods are provided. An exemplary semiconductor structure includes a semiconductor substrate having a plurality of cell regions. Each of the cell regions includes a device region, a protection region surrounding the device region and an isolation region surrounding the device region and the protection region. The semiconductor structure also includes a device structure on the semiconductor substrate in the device region; a protection ring structure on the semiconductor substrate in the protection region; an isolation structure on the semiconductor substrate in the isolation region; a passivation layer on the protection ring structure, the device structure and the isolation structure; and a trench passing through the passivation layer in the isolation region.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: August 17, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation ]
    Inventor: Chun Song
  • Patent number: 11075300
    Abstract: The semiconductor device includes a first insulating layer; a first oxide semiconductor; a first insulator containing indium, an element M (M is gallium, aluminum, titanium, yttrium, or tin), and zinc; a second oxide semiconductor; a source electrode layer; a drain electrode layer; a second insulator containing indium, the element M, and zinc; a gate insulating layer; and a gate electrode layer. The first and second oxide semiconductors each include a region with c-axis alignment. In the first and second oxide semiconductors, the number of indium atoms divided by sum of numbers of the indium atoms, element M atoms, and zinc atoms is ? or more. In the first insulator, the number of zinc atoms divided by sum of the numbers of indium atoms, element M atoms, and zinc atoms is ? or less.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: July 27, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shinpei Matsuda
  • Patent number: 11069511
    Abstract: A system having an auxiliary plasma source, disposed proximate the workpiece, for use with an ion beam is disclosed. The auxiliary plasma source is used to create ions and radicals which drift toward the workpiece and may form a film. The ion beam is then used to provide energy so that the ions and radicals can process the workpiece. Further, various applications of the system are also disclosed. For example, the system can be used for various processes including deposition, implantation, etching, pre-treatment and post-treatment. By locating an auxiliary plasma source close to the workpiece, processes that were previously not possible may be performed. Further, two dissimilar processes, such as cleaning and implanting or implanting and passivating can be performed without removing the workpiece from the end station.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: July 20, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Christopher Hatem, Peter F. Kurunczi, Christopher A. Rowland, Joseph C. Olson, Anthony Renau
  • Patent number: 11049965
    Abstract: A semiconductor device includes a first external electrode with a first electrode surface portion; a second external electrode with a second electrode surface portion; a MOSFET chip with a built-in Zener diode which includes an active region and a peripheral region; a control IC chip which drives the MOSFET chip based on voltage or current between a drain electrode and a source electrode of the MOSFET chip; and a capacitor which supplies power to the MOSFET chip and the control IC chip. The first electrode surface portion is connected to either the drain electrode or the source, the second electrode surface portion is connected to either the source electrode or the drain electrode, a plurality of unit cells of the MOSFET with the built-in Zener diode are provided in the active region, and the breakdown voltage of the Zener diode is set to be lower than that of the peripheral region.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: June 29, 2021
    Assignee: HITACHI POWER SEMICONDUCTOR DEVICE, LTD.
    Inventors: Masaki Shiraishi, Tetsuya Ishimaru, Junichi Sakano, Mutsuhiro Mori, Shinichi Kurita