Abstract: An optical device includes a multilayered GaAs structure including a plurality of sublayers and an optical structure layer on the multilayered GaAs structure, the optical structure layer including a Group III-V compound semiconductor material. The optical structure layer may be, for example, a light-emitting layer having a multi-quantum well structure.

Abstract: An optical semiconductor device includes: a mesa that is provided on a surface in a <011> direction of a semiconductor substrate having a (100) plane orientation and being of a first conductivity type, and includes a first cladding layer of the first conductivity type, an active layer, and a second cladding layer of a second conductivity type; a semi-insulating buried layer that buries both sides of the mesa, is provided on the semiconductor substrate, and includes a first region and a second region farther from the mesa than the first region; an insulation film provided on the first and second regions of the buried layer; and an electrode provided on the mesa and the insulation film on the first region; wherein a surface of the first region is at a height equal to or lower than a surface of the mesa, and lowers at farther distances from the mesa.

Abstract: In an embodiment, the optoelectronic semiconductor component (1) comprises a semiconductor layer sequence (2) with an active zone (22) for generating a radiation. On an bottom side (20) of the semiconductor layer sequence (2) there is an electrically insulating separation layer (3) with several openings (32). An adhesion-promoting layer (4) is located next to the openings (32) on a side of the separation layer (3) facing away from the semiconductor layer sequence (2). A continuous metallization layer (5) is located on a side of the adhesion-promoting layer (4) facing away from the semiconductor layer sequence (2). The semiconductor layer sequence (2) is electrically contacted in the openings (32) directly by the metallization layer (5). The metallization layer (5) and the openings (32) are spaced from the active zone (22) in the direction perpendicular to the separation layer (3).

Abstract: A display device includes a first electrode disposed on a substrate, a first insulating film disposed on the first electrode and having a first opening formed, a second insulating film disposed on the first insulating film and having a second opening, and a contact electrode electrically contacting at least a portion of the first electrode through the first opening and the second opening, wherein a side surface of the first insulating film defines the first opening, and the second insulating film overlaps the side surface of the first insulating film such that the contact electrode and the first insulating film are not in contact with each other.

Abstract: Described are light emitting diode (LED) devices comprising a plurality of mesas defining pixels, each of the plurality of mesas comprising semiconductor layers, an N-contact material in a space between each of the plurality of mesas, a dielectric material which insulates sidewalls of the P-type layer and the active region from the metal. Each of the mesas is spaced so that there is a pixel pitch in a range of from 10 ?m to 100 ?m and dark space gap between adjacent edges of p-contact layer. The dark space gap may be less than 20% of the pixel pitch. The dark space gap may be in a range of from 4 ?m to 10 ?m.

Abstract: Metal interconnect structures are reworked to address possible voids or other defects. Etching of initially deposited interconnect metal to open voids is followed by reflow to accumulate interconnect metal at the bottoms of trenches. Additional interconnect metal is deposited over the initially deposited interconnect metal by electroplating and/or electroless plating. Additional diffusion barrier material may be deposited and patterned prior to deposition of the additional interconnect material.

Abstract: In a method for manufacturing a semiconductor device, a doped region is formed in a substrate from a first main surface. An insulating layer is formed over the doped region of the substrate. Contacts are formed in the insulating layer such that the contacts extend into the doped region. A portion of the substrate is removed from a second main surface. A trench, a first conductive line, and a second conductive line are formed from the doped region of the substrate through etching the substrate from the second main surface. The trench extends through the substrate to expose the insulating layer. The first and second conductive lines are spaced apart from each other by the trench. The contacts are positioned along and in contact with the first and second conductive lines. The trench is filled with a dielectric material.

Abstract: A nanorod light-emitting device is provided. The nanorod light-emitting device includes a first semiconductor layer, a light-emitting layer on the first semiconductor layer, a second semiconductor layer disposed on the light-emitting layer, at least one conductive layer disposed between a central portion of a lower surface of the light-emitting layer and the first semiconductor layer, or between a central portion of an upper surface of the light-emitting layer and the second semiconductor layer, at least one current blocking layer that surrounds a side surface of the at least one conductive layer, and an insulating film that surrounds a side surface of the second semiconductor layer, a side surface of the light-emitting layer, and a side surface of the at least one current blocking layer.

Abstract: A wavelength-converting member includes a wavelength-converting layer, a heat-dissipating component, and a securing member. The wavelength-converting layer has an upper surface, a lower surface, and one or more lateral surfaces with each of the one or more lateral surfaces of the wavelength-converting layer defining an inclined surface inclined at an acute angle with respect to the lower surface of the wavelength-converting layer. The wavelength-converting layer includes a thermally conductive part, and a fluorescent material containing part in contact with the thermally conductive part. The wavelength-converting layer is mounted on the heat-dissipating component. The securing member is secured to the heat-dissipating component. The securing member presses the inclined surface of each of the one or more lateral surfaces such that the wavelength-converting layer is secured to the heat-dissipating component.

Abstract: A system having an auxiliary plasma source, disposed proximate the workpiece, for use with an ion beam is disclosed. The auxiliary plasma source is used to create ions and radicals which drift toward the workpiece and may form a film. The ion beam is then used to provide energy so that the ions and radicals can process the workpiece. Further, various applications of the system are also disclosed. For example, the system can be used for various processes including deposition, implantation, etching, pre-treatment and post-treatment. By locating an auxiliary plasma source close to the workpiece, processes that were previously not possible may be performed. Further, two dissimilar processes, such as cleaning and implanting or implanting and passivating can be performed without removing the workpiece from the end station.

Abstract: A pixelated-LED chip includes an active layer with active layer portions, segregated by streets, that are configured to illuminate different light-transmissive substrate portions to form pixels. A light extraction surface of each substrate portion includes protruding features and light extraction surface recesses that may be formed by sawing. Underfill material may be provided between a pixelated-LED chip and a mounting surface, as well as between pixels and between anodes and cathodes thereof. Certain implementations provide light extraction surface recesses that are non-parallel to each street defined through the active layer. Certain implementations provide light extraction surface recesses that are non-aligned with (e.g., non-parallel to) anode-cathode boundaries of each anode-cathode pair. Such arrangements reduce a likelihood of cracking in portions of a pixelated-LED chip. Methods for fabricating pixelated-LED chips are also provided.

Abstract: An optical device includes a multilayered GaAs structure including a plurality of sublayers and an optical structure layer on the multilayered GaAs structure, the optical structure layer including a Group III-V compound semiconductor material. The optical structure layer may be, for example, a light-emitting layer having a multi-quantum well structure.

Abstract: The present disclosure is directed to anchor structures and methods for forming anchor structures such that planarization and wafer bonding can be uniform. Anchor structures can include anchor layers formed on a dielectric layer surface and anchor pads formed in the anchor layer and on the dielectric layer surface. The anchor layer material can be selected such that the planarization selectivity of the anchor layer, anchor pads, and the interconnection material can be substantially the same as one another. Anchor pads can provide uniform density of structures that have the same or similar material.

Abstract: A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.

Abstract: Methods for forming light emitting diodes (LEDs) that leverage cavity profiles and induced stresses to alter emitted wavelengths of the LEDs. In some embodiments, the method includes forming a cavity on a substrate where the cavity has a cavity profile that is configured to accept an emitter pixel structure for an LED, forming at least one passivation layer in the cavity, and forming at least one optical layer in the cavity on at least a portion of one of the at least one passivation layer. The at least one optical layer is configured to increase a lumen output of the emitter pixel structure. The method further includes forming the emitter pixel structure in the cavity on the at least one optical layer of the emitter pixel structure where the cavity profile is configured to adjust an emitted light wavelength of the emitter pixel structure.

Abstract: A light-emitting element includes a semiconductor layered body including an n-side semiconductor layer having a first region and second regions, a p-side semiconductor layer on the first region, and a light-emitting layer between the first region and the p-side semiconductor layer; an insulating film defining at least one p-side opening above the p-side semiconductor layer and n-side openings each defined above a corresponding second region; an n-side electrode connected to each second region at each corresponding n-side opening; and a p-side electrode electrically connected to the p-side semiconductor layer through the p-side opening. In a top view, the n-side electrode includes at least one base portion on the first region, at least one first extending portion extending in a first direction from the base portion, and at least one second extending portion extending in the first direction from the base portion.

Abstract: A semiconductor device may include a first active fin, a second active fin and a gate structure. The first active fin may extend in a first direction on a substrate and may include a first straight line extension portion, a second straight line extension portion, and a bent portion between the first and second straight line extension portions. The second active fin may extend in the first direction on the substrate. The gate structure may extend in a second direction perpendicular to the first direction on the substrate. The gate structure may cross one of the first and second straight line extension portions of the first active fin and may cross the second active fin.

Abstract: A micro light-emitting device, including a first type semiconductor layer, a light-emitting layer, a second type semiconductor layer, a first type electrode, a second type electrode, and a light reflection layer, is provided. The light-emitting layer is arranged on the first type semiconductor layer. The second type semiconductor layer is arranged on the light-emitting layer. The first type electrode and the second type electrode are both arranged on the second type semiconductor layer. The light reflection layer is arranged between the light-emitting layer and the first type electrode. The light reflection layer includes an oxidized area and a non-oxidized area. A reflectance of the oxidized area is greater than a reflectance of the non-oxidized area. An orthographic projection of a part of the oxidized area on the first type semiconductor layer and an orthographic projection of the first type electrode on the first type semiconductor layer at least partially overlap.

Abstract: A process comprising the following steps of: a) providing a device comprising: a GaN/InGaN structure comprising an electrically conductive doped GaN layer locally covered with InGaN mesas comprising a doped InGaN layer and an undoped or weakly doped InGaN layer, an electrically insulating layer covering the electrically conductive doped GaN layer between the mesas, b) connecting the electrically conductive doped GaN layer and a counter-electrode (500) to a voltage or current generator, c) dipping the device and the counter-electrode into an electrolyte solution, d) applying a voltage or current between the electrically conductive doped GaN layer and the second electrode to porosify the doped InGaN layer, e) forming an InGaN layer by epitaxy on the InGaN mesas, whereby a relaxed epitaxially grown InGaN layer is obtained.

Abstract: In a three-dimensional memory device, an interconnect structure is formed over a substrate and a first deck is formed over the interconnect structure. The first deck includes alternating first insulating layers and first word line layers, and a first channel structure extending through the first stack. The first channel structure has a first channel dielectric region and a first channel layer. The first channel dielectric region is formed along sidewalls of the first channel structure, positioned over a top surface of the interconnect structure, and in contact with the first insulating layers and the first word line layers. The first channel layer is formed along the first channel dielectric region, and includes a rounded projection that extends away from the top surface of the interconnect structure, extends outwards into the first stack at an interface of the interconnect structure, the first channel structure and the first stack.