Abstract: An integrated circuit packaging method and an integrated packaging circuit, the integrated circuit packaging method including: circuit layers are provided on the top surface of a substrate, the bottom surface of the substrate or the interior of the substrate, the circuit layers having circuit pins; the substrate is provided with connection through holes, and the connection through holes are joined up with the circuit pins; a device is placed on the substrate, and the device is provided with device pins on a surface facing the substrate, which makes the device pins join up with a first opening of the connection through holes; conductive layers are fabricated in the connection through holes by means of a second opening of the connection through holes; and the conductive layers electrically connect the device pins to the circuit pins.

Abstract: A photodetector includes: a photoelectric conversion layer including a first principal surface from which light enters and a second principal surface on the opposite side from the first principal surface and configured to perform photoelectric conversion on the light; a first diffraction grating formed on a side of the second principal surface and including a configuration where first surfaces which extend in a stripe state in a first direction and second surfaces which extend in a stripe state in the first direction and have a height difference with respect to the first surfaces are alternately arranged; metal wires provided at intervals over the first surfaces and the second surfaces and which extend in the first direction or a second direction perpendicular to the first direction; and a second diffraction grating formed over the first diffraction grating and including grooves which are formed at intervals and extend in the second direction.

Abstract: Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase Vt. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease Vt. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies Vt. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.

Abstract: A deep ultraviolet light-emitting element of this disclosure includes, in this order, an n-type semiconductor layer; a light-emitting layer; and a p-type semiconductor layer. An emission spectrum of the deep ultraviolet light-emitting element has a primary emission peak wavelength in a wavelength range of 200 nm or more and 350 nm or less, and a blue-violet secondary light emission component having a relative emission intensity of 0.03% to 10% across a wavelength range of 430 to 450 nm, a yellow-green secondary light emission component having a relative emission intensity of 0.03 to 10% across a wavelength range of 540 to 580 nm, when the relative emission intensities are expressed relative to an emission intensity at the primary emission peak wavelength taken as 100%. The ratio of an emission intensity at a wavelength of 435 nm to an emission intensity at a wavelength of 560 nm is 0.5 to 2.

Abstract: A semiconductor device includes a wiring substrate including a first surface, a second surface opposite to the first surface, a first heat dissipation conductive pattern formed on the first surface, a second heat dissipation conductive pattern formed on the first surface, a first wiring formed on the first surface, and a second wiring formed on the first surface. The semiconductor device also includes a semiconductor chip disposed on the wiring substrate and including a third surface and a fourth surface opposite to the third surface. In plan view, the second wiring is adjacent to the first and second heat dissipation conductive patterns without intervening any wiring and any conductive pattern between the second wiring and the first and second heat dissipation conductive patterns.

Abstract: An apparatus comprises an antifuse cell comprising first and second nodes, an antifuse element, and a transistor. The antifuse element and the transistor are coupled in series between the first and second nodes. The antifuse element comprises an antifuse gate. The transistor comprises a transistor gate comprising a substantially-annular structure substantially surrounding the antifuse gate.

Abstract: An optoelectronic module. In some embodiments, the optoelectronic module includes: a substrate; a digital integrated circuit, on an upper surface of the substrate; and a frame, secured in a pocket of the substrate. The pocket is in a lower surface of the substrate, and the substrate includes an insulating layer, and a plurality of conductive traces.

Abstract: A capacitor is provided. The capacitor includes a substrate that has opposing first and second main surfaces. The capacitor also includes at least two conductive plates that are formed in the substrate and extend from the first main surface to the second main surface of the substrate. The capacitor further includes at least one insulating structure that is formed between two adjacent conductive plates of the at least two conductive plates and extends from the first main surface to the second main surface.

Abstract: Aspects of the disclosure provide a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.

Abstract: A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.

Abstract: A semiconductor element capable of adjusting a barrier height ?Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the “change of the barrier height caused by the bias” described above up to a deep degeneration range. An electron Fermi level (EF) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).

Abstract: Reliability of a semiconductor device is improved. In the semiconductor device SA1, a snubber capacitor pad SNP electrically connected to the capacitor electrode of the snubber capacitor is formed on the surface of the semiconductor chip CHP.

Abstract: In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a pad stack over a semiconductor substrate, where the pad stack includes a lower pad layer and an upper pad layer. An isolation structure having a pair of isolation segments separated in a first direction by the pad stack is formed in the semiconductor substrate. The upper pad is removed to form an opening, where the isolation segments respectively have opposing sidewalls in the opening that slant at a first angle. A first etch is performed that partially removes the lower pad layer and isolation segments in the opening so the opposing sidewalls slant at a second angle greater than the first angle. A second etch is performed to round the opposing sidewalls and remove the lower pad layer from the opening. A floating gate is formed in the opening.

Abstract: A display apparatus is provided. The display apparatus includes a display substrate and a plurality of pads arranged above the display substrate. Each of the plurality of pads includes a first conductive layer, at least a portion of which is covered by an insulating film, a second conductive layer arranged above the first conductive layer, and a clamping portion formed in the second conductive layer.

Abstract: Semiconductor devices including bamboo tall via interconnect structures and methods of forming the bamboo tall via interconnect structures generally include a first via in a first dielectric layer including a liner layer and a bulk conductor in the first via, wherein the bulk conductor includes a recess filled with a conductive metal different from the bulk conductor and selected to prevent diffusion of the bulk conductor. At least one additional via is in a second dielectric layer including a liner layer and a bulk conductor in the least one additional via, wherein the second dielectric layer is on the first dielectric layer, and wherein the bulk conductor includes a recess filled with a conductive metal different from the bulk conductor and selected to prevent diffusion of the bulk conductor. The at least one additional via is aligned with the first via.

Abstract: A carrier film according to an embodiment of the present invention comprises: a base film; and a first adhesive layer formed on a surface of the base film such that an element to be transferred is attached to the first adhesive layer, wherein the magnitude of force of adhesion between the element and the first adhesive layer is in proportion to the depth of press-fitting at which the element is press-fitted into the first adhesive layer.

Abstract: The present disclosure is directed to anchor structures and methods for forming anchor structures such that planarization and wafer bonding can be uniform. Anchor structures can include anchor layers formed on a dielectric layer surface and anchor pads formed in the anchor layer and on the dielectric layer surface. The anchor layer material can be selected such that the planarization selectivity of the anchor layer, anchor pads, and the interconnection material can be substantially the same as one another. Anchor pads can provide uniform density of structures that have the same or similar material.

Abstract: A structure including a first layer of one or more molecular components having a first top anchor group, a first functional moiety and a first bottom anchor group. The first functional moiety connects the first top anchor group to the first bottom anchor group. The structure further includes a first conductive film of one or more nanoparticles disposed on the first layer of one or more molecular components. Each of at least a portion of the one or more nanoparticles bond with the first top anchor group of the one or more molecular components. Each of at least a portion of the one or more nanoparticles cross-link with at least one other of the nanoparticles. The first conductive film forms a first contact for the first layer of one or more molecular components.

Abstract: Devices and techniques are disclosed herein which include a die including side surfaces such that light emitted from the die can exit through the side surfaces. The die includes a first surface and a second surface opposite the first surface such that the distance between the first surface and the second surface is at least 100 micro meters. The die also include a wavelength converting material deposited external to the die such that the wavelength converting material covers the side surfaces. The wavelength converting material includes phosphor particles, a transparent risen carrier, and transparent particles configured to increase the volume of the wavelength converting material, the transparent particles having a refractive index (RI) that is similar to the RI of the transparent risen carrier.

Abstract: A display panel and a display device are provided. The display panel includes a substrate, a plurality of signal lines, a plurality of fan-out lines, and a resistance balance member. The substrate defines a display area and a fan-out area. The signal lines are defined in the display area, and the fan-out lines are defined in the fan-out area and are electrically communicated with the signal lines. The fan-out area defines a central winding line region and a peripheral straight line region. The resistance balance member is connected to one fan-out line of the peripheral straight line region in series.