Abstract: A scalable memory controller for use in connection with error correction code is provided. According to the invention, the channels of the controller are interconnected to a plurality of parity engines and associated cache memories using a switched fabric architecture. A processor is provided for allocating operations requiring access to the parity engines or cache memories. By providing multiple parity engines and cache memories, error correction syndrome values can be calculated in parallel. The performance of the controller can be selectively scaled by providing a greater or lessor number of parity engines and associated cache memories. Furthermore, by utilizing a switched fabric internal architecture, data transfers between the internal components of the controller can be conducted simultaneously.

Abstract: A cache for AGP based computer systems is provided. The graphics cache is included as part of a memory bridge between a processor, a system memory and a graphics processor. A cache controller within the memory bridge detects requests by the processor to store graphics data in the system memory. The cache controller stores the data for these requests in the graphics cache and in the system memory. The cache controller searches the graphics cache each time it receives a request from the graphics controller. If the a cache hit occurs, the cache controller returns the data stored in the graphics cache. Otherwise the request is performed using the system memory. In this way the graphics cache reduces the traffic between the system memory and the memory bridge, overcoming an important performance bottleneck for many graphics systems.

Abstract: A method and system for implementing a mirror addressing scheme in conjunction with a symmetrical data table are disclosed. The method includes receiving a first address. In response to determining that the first address corresponds to an upper portion of a data table, generating a second address from the first address, where the second address corresponds to a lower portion of the data table. The method further includes using the second memory address to access a memory array, whereby data corresponding to the upper portion of the data table is accessed from the lower portion of the data table. In one embodiment, determining that the first address corresponds to an upper portion of the data table is achieved by determining upper segment and lower segment boundaries for the first memory address determining that the most significant bit of the lower segment is asserted.

Abstract: A Page Address Look-up Range RAM is disclosed which allows for individual comparisons to be made on a number of consecutive addresses. The upper bits of the bus address 410 (often representing a “page”) are compared against one or more reference registers 430-437 to yield one or more “match_high”s. The lower bits of the same bus address 420 are used to look-up the value of “match_low” in a Page Look-Up RAM 440, the bit of interest corresponding to the particular “match-high” reference register i.e. 430. If both the “match_high” and “match_low” events are true, or=1, then the bus address has matched and should cause the event, otherwise not. The most cost effective implementations will have a Look-up RAM 440 with a width of a multiple of 8. This will allow comparison of the bus address against a multiple of individual pages.

Abstract: A bit-parallel system and method for allocating storage space for data objects using a bitmap. It is determined whether a suffix of free space bits in a previous bitmap word can be used with a prefix of free space bits in a current word that is contiguous to the previous word. If so, this renders a string of free space bits spanning multiple words, and it is determined whether the string represents a sufficiently large number of contiguous blocks (“the target”) to store the data object. If not, it is determined whether sufficient contiguous free space bits in the current word exist to fulfill the target. If the target still can't be achieved, the longest suffix of free space bits in the current word is found for possible use with the prefix of the next contiguous word, and the next word is then retrieved and processed. The algorithm for finding the suffix preferably is undertaken by considering bits in parallel.

Abstract: A cache memory having a mechanism for managing cache lines replacement is disclosed. The cache memory comprises multiple cache lines partitioned into a first group and a second group. The number of cache lines in the second group is preferably larger than the number of cache lines in the first group. A replacement logic block selectively chooses a cache line from one of the two groups of cache lines for replacement during an allocation cycle.

Abstract: A processor-implemented method is described for updating a datum stored in a nonvolatile memory, bits of which cannot be overwritten from a first logical state to a second logical state without a prior erasure. A first storage location in the memory that stores a first version of the datum is accessed. A status field of the first storage location is checked to determine whether the first version of the datum has been superseded. If the status field of the first storage location indicates that the first version of the datum has not been superseded, then a most recent version of the datum is stored in a second storage location of the memory. An address of the second storage location is then written into a next location address field of the first storage location and the status field of the first storage location is written to indicate that the first version of the datum has been superseded such that the datum is updated without the prior erasure of the memory.

Abstract: A system and method for replacing cached data for a computer system utilizing one or more storage devices is disclosed. The storage devices are divided into a plurality of areas or bins. Each bin is preferably the same size. A Window Access Table (WAT) is an array stored in memory that contains all the time windows for each bin. Each time window holds a frequency value corresponding to the number of times the bin has been accessed during the time period corresponding to that time window. A hot spot algorithm is used to calculate a hot spot value hsf(x) for each bin based on its associated frequency values listed in the WAT. The hot spot algorithm uses scaling coefficients to weight the frequency values based on the time window. Each line in cache will therefore have an associated bin for which a hot spot value hsf(x) has been calculated. This data may be stored in a hot spot table.

Abstract: Apparatus for supplying multiple, separately addressed data items from a data table in external memory. The apparatus comprises a cache memory (230) having n separately addressable memories banks organised as m cache-lines and n programmable address generators (1881) each coupled to a corresponding one of said n memory banks. The generators (1881) using an index to generate multiple addresses to simultaneously retrieve multiple data items from the memory banks. A data organizer (1892) positions the retrieved data in an output packet.

Abstract: A method and computer program for allocating storage for a header and one or more data elements in a data storage facility are disclosed. The method and computer program include computing a hole size B that is a portion of a word that would be unallocated if storage were allocated to the header and to the data elements in a preferred order. The method and computer program include finding a subset of data elements S={Fi1, Fi2, . . . , Fin} that satisfy the equation (SizeModN(Fi1)+SizeModN(Fi2)+ . . . +SizeModN(Fin))mod N=B where N is the largest alignment requirement associated with any data element. The method and computer program include allocating storage to data elements in S first and allocating storage to the remaining elements in the preferred order. A lookup table and a method for building the lookup table are also disclosed.

Abstract: An automated data storage library stores logical volumes, including logical volumes to be copied to a second library, in cache storage, and migrates logical volumes to physical media volumes stored on storage shelves. In response to a request for recalling one of the logical volumes to be copied to cache, a library controller first determines which physical media volume contains the requested migrated logical volume. The library controller identifies all of the logical volumes to be copied that are migrated and stored as stacked logical volumes on the physical media volume containing the requested migrated logical volume; selects up to “N” of the identified logical volumes, including the requested migrated logical volume; and may arrange a selection list of the selected logical volumes in a sequence in accordance with the order that the logical volumes are written on the physical media volume.

Abstract: A selection circuit causes either a memory 6H or 6L to enter an enabled state according to address data A16 of address data A0-A16 when a mode signal M is 1. The selection circuit comprises OR gates (10, 12) which output different outputs. When the address data A16 is 0, a nonvolatile memory 6L enters an enabled state. Then, the memory 6L is addressed according to the address data A0-A15 so that, for example, 8-bit lower data is written therein. On the other hand, when the address data A16 is 1, a nonvolatile memory 6H becomes in an enabled state. Then, the memory 6H is addressed according to the address data A0-A15 so that, for example, 8-bit upper data is written therein. Also, when an external terminal (17) is grounded, and a mode signal become 0, the OR gates (10, 12) outputs signals 0, so that the memories 6H, 6L simultaneously become in an enabled state. When data is read from corresponding addresses of each memory, data of, for example, 16-bits is obtained.

Abstract: A dynamic address mapping technique eliminates contention to memory resources of a symmetric multiprocessor system having a plurality of processors arrayed as a processing engine. The technique defines two logical-to-physical address mapping modes that may be simultaneously provided to the processors of the arrayed processing engine to thereby present a single contiguous address space for accessing individual memory locations, as well as memory strings, within the memory resources. These addressing modes include a bank select mode and a stream mode.

Abstract: A computer system for flashing Extended System Configuration Data (ESCD) and associated variables to a flash read-only memory (ROM) is provided. During Power-On-Self-Test (POST) code, a ROM image is copied from an ESCD sector of a read-only memory to an ESCD original buffer and an ESCD write buffer. The ESCD write buffer may be updated by POST code. Following the POST operations, the contents of the ESCD write buffer are copied to an ESCD runtime buffer. The contents of the ESCD original buffer or the ESCD sector are compared to the contents of the ESCD runtime buffer. If the contents of the ESCD runtime buffer differ from the contents of the compared buffer or sector, SMI code flashes the ROM image in the ESCD runtime buffer to the flash ROM. If the ESCD runtime buffer is the same as the contents of the compared buffer or sector, a ROM flash it not performed. POST is then exited and the computer system is booted.

Abstract: A processor for performing calculations based on an instruction code, the number of bits of which is not an integer multiple of a byte. The instruction code is divided into higher order bits and lower order bits. The number of the lower order bits is an integer multiple of one byte. A memory stores the lower order bits in a lower order bit storage section and the higher order bits in a higher order bit storage section. The lower order bits and the corresponding higher order bits are read from the memory in the same cycle when generating the instruction code.

Abstract: The disk array controller includes a plurality of interfaces with respective processors for connecting with a host computer or disk devices, duplicated shared memories connected in a one to one ratio between each interface and respective access paths, a selector connected to the plurality of interfaces, and a cache memory connected to the selector. The number of access paths between the selector and the plurality of interfaces is greater than the number of access paths between the cache memory and the selector. Each processor performs dual writing in the duplicated shared memories.

Abstract: A disk-based storage system for storing a plurality of data segments responds to a direction-selection signal by autonomously providing the data segments in a selected sequence so as to be concatenated together to define a continuous data stream. The disk-based storage system comprises nonvolatile storage including rotating disk media having a plurality of addressable locations. Each of the data segments is stored in a respective one of the addressable locations. Each of the addressable locations has a leading end and a trailing end. A first one of the addressable locations has a trailing end on a first track, and a second one of the addressable locations has a leading end on a second track, the second track being spaced from the first track. The non-volatile storage provides for locally storing a doubly-linked list of pointers.

Abstract: The present invention is directed to a system and method for synchronizing data between mirrored subsystems. A method for storing data may include receiving data suitable for storage to a first storage device and a second storage device, wherein the first storage device and the second storage device are mirrored. A map is created including at least one map entry having an identifier suitable for describing a range of addressable data blocks, wherein the map entry corresponds to a data block modified after operation of the first storage device is suspended. A map is stored including the at least one map entry on the second storage device, wherein the map is suitable for being utilized to restore data stored on the second storage device to at least one of the first storage device and a third storage device.

Abstract: A method for transferring data from a large capacity data storage device to a host machine. The method requires the attachment of a plurality of SRAM memory blocks to an optical disk reader. Each SRAM memory block is used as temporary storage area got a sector of data so that data can be proofread one sector at a time. As soon as the entire sector is checked and corrected, the error-free data is transferred to an external DRAM memory. Thereafter, correct data can be read from the DRAM by the host machine at any time. The internal SRAM memory serves as a buffer holding sectors of data so that error detection and error correction of individual sector can be carried out. Additionally, the external DRAM memory serves as a buffer holding the correct data for the host machine.

Abstract: An invariant numeric reference format is defined in a run-time environment for both run-time and storage use. A numeric reference to an object encodes the location of the object as an integral offset from an implicit machine pointer. In environments where the size of contiguous virtual memory segments is limited, objects are stored in a number of fixed-size contiguous chunks in virtual memory called pages. A page-offset numeric reference includes an offset and a page number, which is used to index a page map that contains a page pointer to the beginning of the page. Page-offset numeric references are dereferenced by adding the offset in the numeric reference to the page pointer obtained from the page map based on the page number in the numeric reference.