Abstract: The present invention provides a multi-function buffer system for use in a peripheral storage device system, as well as a peripheral storage device system having a multi-function buffer system. The buffer system comprises a multi-purpose memory component which may be adapted for use as scratchpad and/or instruction storage accessible by a controller processor, as well as for buffering information being transferred between the peripheral storage device and a host computer system.

Abstract: A spare area management method of an optical recording medium is disclosed. The spare area management method utilizes an identification information to indicate whether a primary spare area is full or a supplementary spare area has been assigned or extended, as necessary. Also, the present spare area management method improves the performance of the driver by replacing a defect block with a spare block nearer to the defect block.

Abstract: The data storage array apparatus having a RAID configuration according to the present invention comprises an internal access issuance part 10 which issues internal access requests to data storage parts 6, a group response monitoring part 11 which monitors processing responses in the data storage parts 6 until an internal access requesting group satisfies a predetermined condition and issues a notice of completion of monitoring, an external access response part 12 which notifies to outside of completion of external access in response to a predetermined situation, a continuous response monitoring part 13 which further continuously monitors, based on the notice of completion of monitoring, processing responses for each HDD with respect to an internal access request which was met with no processing response from the data storage parts, and an array operation control part 14 which controls, based on continuous response monitoring information from the continuous response monitoring part, issuance of internal access

Abstract: Embodiments of the present invention provide a pre-decoder in a front-end system provided between an instruction cache and a decoder. The front-end system may toggle between two modes of operation. In a first mode, called the “fast mode” the front-end system retrieves pre-decoded instructions from the instruction cache and decodes them directly. In a second mode, called the “marking mode,” the front-end system retrieves data from the instruction cache and synchronizes to them prior to decoding. Synchronization results may be stored back in the instruction cache for later use.

Abstract: A disk array controller connected in a star configuration with a plurality of interfaces each having a processor, a shared memory connected to the interfaces by access paths and a common bus connected to the interfaces. The shared memory transmits interruption signals to the interface by way of control signals when one of the processors writes broadcast data into the shared memory.

Abstract: An apparatus and method for performing speculative directory cache tag updates for read accesses to memory is herein disclosed. A control unit for performing tag updates is coupled between the memory controller and the memory bank in a multiprocessor system that employs a directory-based coherency protocol. The control unit transmits data read from the memory bank to the memory controller while calculating the updated tag that it then writes back to the memory bank. In this manner, the memory bank busy time and memory bus traffic are reduced thereby improving the overall performance of a memory access.

Abstract: A prevalidation content addressable memory, CAM, is used to pre-decode a virtual address region extension and enable it for use by a translation look-aside buffer, TLB. The prevalidation CAM removes the region extensions stored in region registers from a serial TLB look-up path.

Abstract: A modulus address generator calculates the next address to access from a current address of a circular buffer having a length L and an address shift from the current address to the next address to access. Within the circuit of the modulus address generator, a plurality of registers stores the length L of the circular buffer, the current address, and the address shift. A separator circuit generates an offset address and a base address from a mask value and the current address. A modulus calculation via a plurality of adders, and selectors is performed to calculate the next address of the circular buffer to access. A sign selector associated with an inverter and the separator circuit sets a wrap around flag depending on whether a wrap around the circular buffer has occurred during the modulus calculation of the next address to access.

Abstract: An information processing system has a plurality of modules, including a processor, a main memory and a plurality of I/O devices. A data cache comprises a cache data memory which is coupled to the processor which provides data to the processor in response to a load operation and for writing data from the processor in response to a store operation. A refill controller is coupled to the cache data memory for controlling the operation of the data cache in accordance with a specifiable policy. An external access controller is coupled to the cache data memory. The external access controller is coupled to an external memory bus, such that the contents of the cache data memory are accessible for read and write operations in response to read and write requests issued by the modules in the information processing system.

Abstract: The circuit handles access contentions in memories with a plurality of mutually independent, addressable I/O ports. There are provided two subcircuits, namely the so-called contention identification circuit and the so-called access inhibit circuit. The contention identification circuit identifies an access contention between two or more ports and generates a status signal. This status signal is communicated to the contention inhibit circuit. The contention inhibit circuit allocates a priority to each of the ports which are involved in the access contention. Based on the prioritization, the highest prioritized port is enabled, while the remaining ports are inhibited (temporarily disabled). The prioritization proceeds according to a predetermined algorithm. Two specific prioritization algorithms are given, namely a simple so-called PIH algorithm, in which the ports are hierarchically designated and a so-called “fair” IPIH algorithm.

Abstract: A microprocessor is equipped with an address translation mechanism for performing dynamic address translation from a virtual address to a physical address on a page-by-page basis. The microprocessor includes a large-capacity low-associativity address translation buffer, and is capable of avoiding limitations imposed on a TLB entry lock function, while reducing the overhead for address translation. The address translation mechanism comprises an address translation buffer having an entry lock function, and control logic for controlling the operation of the address translation buffer. The address translation buffer includes a lower-level buffer organized as a lower-level hierarchy of the address translation buffer and having no entry lock function, and a higher-level buffer organized as a higher-level hierarchy of the address translation buffer and having an entry lock function, the higher-level buffer having higher associativity than the associativity of the lower-level buffer.

Abstract: A backup memory for constituent packages constituting a transmission system for communication stores a key code identifying the package and configuration data for the package. The constituent packages can be started in a parallel manner based on key code comparison performed between a main CPU and the package so that the time required to start the package is reduced.

Abstract: A method and apparatus for providing passed pointer detection in audio/video streams on disk media. The present invention sets up an audio/video stream on a disk drive, uses read and write commands for accessing contiguous data and provides a pointer system that provides a warning when manipulating the pointers during fast forward and reverse functions that one pointer has passed the other. The position of a first pointer and a second pointer in at least one stream is monitored during a command execution. A determination is made when the positions of the first and second pointers cross to create a passed pointer state. An indicator is set to signal that a passed pointer state has occurred. The passed pointer indicator is then used to prevent anomalous behavior in processing of the at least one stream.

Abstract: In the storage device, a buffer memory stores a command queue consisting of a plurality of commands received from a host. A control section searches a command to be executed next to a command which is being executed from the command queue according to a predetermined condition, and then performs rearrangement of the commands in the command queue such that. The predetermined condition is that, the time required to move the head, which head performs reading/writing on the magnetic disk, to the magnetic disk after the execution of the command which is being executed is finished is not longer than a predetermined time.

Abstract: The present invention is embodied in the disk drive having a cache control system that is configured to efficiently respond to host commands by forming variable length segments of memory clusters for caching disk data in contiguous ranges of logical block addresses without regard to the sequential order of the memory clusters. The cache control system has a tag memory usable only for defining the segments. The tag memory has a plurality of tag records pointing to cluster control blocks associated with the memory clusters for defining the segments. The tag memory may be accessed and updated by several state machines in the cache control system and by a microprocessor in the disk drive.

Abstract: An apparatus and method within a pipeline microprocessor are provided for allocating a cache line within an internal data cache upon a write miss to the data cache. The that apparatus and method allow data to be written to the allocated cache line before fill data for the allocated cache line is received from external memory over a system bus. The apparatus includes write allocate logic and a write buffer. The write allocate logic allocates the cache line within the data cache, it stores data corresponding to the write miss within the allocated cache line, and queues a speculative write command directing an external bus to store said the data to the external memory in the event that transfer of the fill data is interrupted. The speculative write command is stored in the write buffer and, in the event of an interruption such as a bus snoop to the allocated cache line, the write buffer issues the speculative write command to the system bus, thereby writing the data to external memory.

Abstract: A technique for encoding index values of asynchronous pointers for a non-power-of-two sized buffer that supports the unit distance property. The technique includes converting N+1 pointer index values corresponding to index locations 0 through N of the buffer from the natural binary-coded decimal format to a unit distance code format such as the gray code, adding a 0 bit in the MSB position of each of the N+1 converted pointer index values, adding a first pointer index value at index location N+1 equal to the pointer index value at index location N except that a 1 bit replaces the 0 bit in the MSB position, and adding a plurality of pointer index values at index locations greater than N+1 but less than or equal to N+n+1 that are equal to the first added pointer index value, where “n” equals the number of bits in each pointer index value prior to conversion.

Abstract: A data cache in an in-order single-issue microprocessor that detects cache misses generated by instructions behind a stalled instruction in the microprocessor pipeline and issues memory requests on the processor bus for the missing data so as to overlap with resolution of the stalled instruction, which may also be a cache miss, is provided. The data cache has pipeline stages that parallel portions of the main pipeline in the microprocessor. The data cache employs replay buffers to save the state, i.e., instructions and associated data addresses, of the parallel data cache stages so that instructions above the stalled instruction can continue to proceed down through the data cache and access the cache memory to generate cache misses. The data cache restores the data cache pipeline stages upon detection that stall will terminate. The data cache also detects TLB misses generated by instructions subsequent to the stalled instruction and overlaps page table walks with the stall resolution.

Abstract: A processor employing a dependency link file. Upon detection of a load which hits a store for which store data is not available, the processor allocates an entry within the dependency link file for the load. The entry stores a load identifier identifying the load and a store data identifier identifying a source of the store data. The dependency link file monitors results generated by execution units within the processor to detect the store data being provided. The dependency link file then causes the store data to be forwarded as the load data in response to detecting that the store data is provided. The latency from store data being provided to the load data being forwarded may thereby be minimized. Particularly, the load data may be forwarded without requiring that the load memory operation be scheduled.

Abstract: A cache architecture is adapted to store data items of variable length. Given appropriate circumstances, the cache architecture permits multiple data items to be retrieved from the cache in single clock cycle. The cache architecture may find application in a front end processing system of a processor storing instruction segments. If a first instruction segment does not occupy the full width of the cache, other instruction segments can be retrieved from the cache simultaneously with the first instruction segment. The cache may be organized into a plurality of cache banks, each cache bank being independently addressed. Each bank may consist of several cache ways.