Abstract: It is an object of the present invention to provide a semiconductor integrated circuit having a chip layout that reduces line length to achieve faster processing. A cache comprises a TAG memory module and a cache data memory module. The cache data memory module is divided into first and second cache data memory modules which are disposed on both sides of the TAG memory module, and input/output circuits of a data TLB are opposed to the input/output circuit of the TAG memory module and the input/output circuits of the first and second cache data memory modules across a bus area to reduce the line length to achieve faster processing.

Abstract: A system and a method provides for flexible storage of digital data in a networked-computer system by unifying distribute data storage locations. The system and method allow an e-application operating at a network site, such as an Internet Web site, to utilize distributed storage devices that reside at remote client locations for storing data resulting from execution of the e-application. In an embodiment, the system includes a storage proxy and registry that attempts to “discover” storage at the e-application site or at the remote client locations. The storage proxy and registry may use various routines and algorithms to determine where data should be stored. Alternatively, the system may use a default storage location. In this alternative, the system may require the remote client location to store all or part of the data associated with the e-application.

Abstract: A reassign process is provided in a disk drive system including a plurality of tracks for storing data, each of the tracks being divided into a plurality of sectors, each sector having a corresponding logical address value associated therewith. Each track has a corresponding skew associated therewith and having a nominal skew value providing adequate time for sequential access of the corresponding track from a sequentially preceding track. The reassign process is operative to reassign data sectors stored in a reassign span including a first partial track having a reassign sector, a second partial track having a spare sector corresponding with the reassign sector, and at least one intermediate track disposed between the first and second partial tracks.

Abstract: In a computing system implementing a virtual memory system having real memory storage frames for storing virtual pages of data and an auxiliary storage system comprising auxiliary storage slots for storing copies of corresponding virtual pages, wherein I/O mechanisms are employed for effectuating transfer of data between auxiliary and real storage, a system and method for managing storage of unvirtualized dataset pages destined for auxiliary storage in a manner so to avoid I/O operations when assigning or moving VIO dataset data. The system and method is used to allow faster access to VIO data set pages by allowing that data to be kept in real storage.

Abstract: A data processing system and method are disclosed for storing logical volume information used by a logical volume manager to create and manage a logical volume. The data processing system includes a plurality of storage devices. A plurality of physical partitions within the plurality of storage devices are specified. Each one of the physical partitions includes a plurality of sectors. The specified physical partitions are logically combined to create the logical volume. A first plurality of the sectors are reserved in each of the physical partitions for the logical volume information. The first plurality of sectors are located at the top of each of the physical partitions. The logical volume information is stored in the first plurality of sectors in each of the physical partitions. In this manner, the logical volume information is stored at the top of each of the physical partitions.

Abstract: A lower level cache detects when a line of memory has been evicted from a higher level cache. The lower level cache stores the address of the evicted line. When the system bus is idle, the lower level cache initiates a transaction causing all higher level caches to invalidate the line. The lower level cache then places the line into a special state. If a line in the special state is evicted from the lower level cache, the lower level cache knows that the line is not cached at a higher level, and therefore a back-invalidate transaction is not needed.

Abstract: A system and method for eliminating excessive spin conditions on systems implementing a LRU algorithm. This is achieved by limiting the amount of time a LRU task is allowed to run in any one invocation. If this time limit is exceeded before the LRU task has completed its processing, the LRU task will reschedule itself to run after a short time interval, record which frames have been processed so far, release its serialization resources, and exit to open a window of enablement. During this window, other processes that were spinning for the serialization resources can have a chance to run. When the LRU task runs again it will re-obtain the serialization resources and continue processing frames that were not previously processed. The above process will be repeated until all the appropriate frames in the system are in LRU order.

Abstract: A processor is described which includes a stride detect table. The stride detect table includes one or more entries, each entry used to track a potential stride pattern. Additionally, each entry includes a confidence counter. The confidence counter may be incremented each time another address in the pattern is detected, and thus may be indicative of the strength of the pattern (e.g., the likelihood of the pattern repeating). At a first threshold of the confidence counter, prefetching of the next address in the pattern (the most recent address plus the stride) may be initiated. At a second, greater threshold, a more aggressive prefetching may be initiated (e.g. the most recent address plus twice the stride). In some implementations, the prefetch mechanism including the stride detect table may replace a prefetch buffer and prefetch logic in the memory controller.

Abstract: A cache includes an error circuit for detecting errors in the replacement data. If an error is detected, the cache may update the replacement data to eliminate the error. For example, a predetermined, fixed value may be used for the update of the replacement data. Each of the cache entries corresponding to the replacement data may be represented in the fixed value. In one embodiment, the error circuit may detect errors in the replacement data using only the replacement data (e.g. no parity or ECC information may be used). In this manner, errors may be detected even in the presence of multiple bit errors which may not be detectable using parity/ECC checking.

Abstract: The cache memory is particularly suitable for processing images. The special configuration of a memory field, an allocation unit, a write queue, and a data conflict recognition unit enable a number of data items to be read out from the memory field simultaneously per cycle, in the form of line or column segments. The format of the screen windows that are read out can change from one cycle to another. With sufficient data locality, time-consuming reloading operations do not damage the data throughput since the access requests are pipelined.

Abstract: A programmable nonvolatile memory apparatus having a simplified circuit structure that eliminates a built-in sequencer circuit using a register (102) as a source of generating control signals required for writing data in and erasing data from an EEPROM (101). The register (102) is provided from outside a microcomputer (10) with a register address value inputted through an address bus (103), and a data value inputted through a register bus (104), and also register control signals, such as, a register write signal (105), a register read signal (106) and a register reset signal (107). The register (102) includes flip-flops. From the flip-flops, address data and rewriting data are outputted through buses (115, 116), and in addition, PRPM control signals (108 to 111, 117 and 118) are also outputted. The address space of the register (102) and the address space of the EEPROM (101) are separated from each other.

Abstract: A disk controller includes memory that is accessible by both a microprocessor and hardware parity logic. Parity-related operations are identified by scenario, and parity coefficient subsets are stored in a memory table for each different parity-related calculation scenario. To perform a particular parity-related operation, the microprocessor determines the operation's scenario and identifies the corresponding coefficient subset. The hardware parity logic is then instructed to perform the appropriate parity computation, using the identified coefficient subset. Parity segments are calculated by a parity segment calculation module that is embodied as an application specific integrated circuit (ASIC).

Abstract: A system and method for caching objects using a cost-based publish and subscribe paradigm, wherein a server computing node determines whether a given cache node should receive a cache update based on, e.g., the cost of sending the update. In one aspect, a method for maintaining objects in a cache comprises the steps of issuing a subscription for an object, maintaining a metric for the object; and determining, based on the metric, whether a cache is to receive an update message associated with the object. The metric is preferably correlated with one or more factors such as an importance factor of maintaining the cached copy of the object current, the cost of the sending the update message, and/or the estimated lifetime of the object.

Abstract: The present invention is system and method for determining information that is to be prefetched in a multi-stream environment which can detect sequential streams from among the aggregate reference stream and yet requires relatively little memory to operate, which is uniquely adapted for use in a multi-stream environment, in which multiple data accessing streams are performing sequential accesses to information independently of each other. A reference address referencing stored information is received. A matching run is found. A count corresponding to the run is updated. If the count exceeds a predetermined threshold, an amount of information to prefetch is determined. If a predetermined fraction of the determined amount of information to prefetch must still be retrieved, the determined amount of information is retrieved. A matching run may be found by searching a stack comprising a plurality of entries to find an entry corresponding to the reference address.

Abstract: A computer system with mechanisms for avoiding mapping conflicts in a translation look-aside buffer. A memory manager in the computer system allocates a virtual address to a process by determining a set of previously allocated virtual addresses for the process and selecting the virtual address such that the mapping of the virtual address to the translation look-aside buffer does not conflict with any of the previously allocated virtual addresses.

Abstract: A computer system for storing data includes a host computer having system RAM associated with the computer system, and a file directory peripheral bus connected to the host computer. A mass memory storage peripheral computer device is connected to said peripheral bus, the mass memory storage peripheral computer device having access to the file directory to locate data on the mass memory storage peripheral computer device.

Abstract: A virtual machine object memory structure includes a contiguous region of virtual address space in which objects (i.e., temporary objects) are segregated into a new generation space and an old generation space according to the ages of the objects, as well as a permanent object memory (POM) generation space. The POM generation space operates as a persistent object cache that is not subject to conventional garbage collection processes. The lifetime of an object in the POM generation space relates to the frequency at which objects are copied from a persistent object store (e.g., disk storage) and shared object cache, rather than garbage collection processes relating to the new generation space and the old generation space.

Abstract: A method, system, and computer program product for enforcing logical partitioning of a shared device to which multiple partitions within a data processing system have access is provided. In one embodiment, a firmware portion of the data processing system receives a request from a requesting device, such as a processor assigned to one of a plurality of partitions within the data processing system, to access (i.e., read from or write to) a portion of the shared device, such as an NVRAM. The request includes a virtual address corresponding to the portion of the shared device for which access is desired. If the virtual address is within a range of addresses for which the requesting device is authorized to access, the firmware provides access to the requested portion of the shared device to the requesting device. If the virtual address is not within a range of addresses for which the requesting device is authorized to access, the firmware denies the request.

Abstract: A content address memory (CAM) device that implements a read text highest priority or “RNHPM” instruction. The CAM device initially searches its CAM locations for a match with comparand data. If multiple matches are identified, then the CAM device initially outputs the highest priority matching address. The CAM device may output the highest priority matching address in the same system or a later clock cycle in which the compare instruction was provided. The CAM device may also output data stored in one or more of the CAM cells located at the highest priority matching location and/or status information including the match flags, a full flag, validity bits (e.g., skip and empty bits), and other status information. An RNHPM instruction may then be provided to the CAM device in the next clock cycle or a later clock cycle and cause the next highest priority matching address to be output by the CAM device.

Abstract: An apparatus is described for interleaving bank and page access to a multibank memory device, such as an SDRAM or SLDRAM. An address detector detects a pending page access, and the associated data transfer request is then stored in a page hit register. A control timing chain includes a rank register queue with a bank access input, a page write input, and a page read input. Comparator circuitry provides bank address comparisons to avoid bank conflicts and to control the timing of insertion of the page hit register contents into the appropriate page write or page read input. While a pending page access request is stored in the page hit register, other pending bank access operations can be initiated. Consequently, bank and page accesses can be interleaved in substantially contiguous command cycles, and data transfer bandwidth is correspondingly improved.