Abstract: A method of routing interconnects of a field programmable gate array including: a plurality of logic tiles, and a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects to interconnect logic tile networks of the logic tiles, the method comprises: routing a first plurality of tile-to-tile interconnects in a first plurality of logic tiles. After routing the first plurality of tile-to-tile interconnects, routing a second plurality of tile-to-tile interconnects in a second plurality of logic tiles. The start/end point of each tile-to-tile interconnect in the first plurality and the second plurality of tiles is independent of the start/end point of the other tile-to-tile interconnects in the first and second plurality, respectively.

Abstract: The present disclosure provides an electronic device, a mobile terminal and an antenna assembly. The electronic device includes: a case defining an accommodating groove; a movable support slidably connected to the case, and capable of moving out of or retracting into the accommodating groove; and a first antenna installed on the movable support. Since the first antenna may be ejected out of the accommodating groove along with the movable support, influence of other components disposed inside the electronic device on the first antenna may be reduced. Thus, the implementation of the present disclosure may improve antenna performance of the electronic device.

Abstract: A level converter for a vehicle control device, including: a first voltage terminal; a second voltage terminal; at least one output terminal; an input terminal; a first switch for switching a first current path between the first voltage terminal and the at least one output terminal or one of the output terminals; and a second switch for switching a second current path between the second voltage terminal and the at least one output terminal or another of the output terminals; the first and second switches being switchable in response to different levels at the input terminal so that when a first level is present at the input terminal, the first switch is closed and the second switch is open, and so that when a second level is present, the first switch is open and the second switch is closed. Also described is a related control device, utility vehicle and method.

Abstract: Methods, systems, and apparatus for individual qubit excitation control with a global excitation drive. In one aspect, a method includes accessing a quantum system that comprises a plurality of qubits; a plurality of qubit frequency control lines, each qubit frequency control line corresponding to an individual qubit and controlling the frequency of the qubit; a driveline; a plurality of couplers, each coupler coupling a corresponding qubit to the driveline so that a plurality of qubits are coupled to the driveline; determining one or more qubits that require a rotation operation; for each qubit requiring a rotation operation: tuning the qubit frequency to the corresponding driveline frequency of the rotation operation; performing the rotation operation using a microwave pulse on the excitation drive; and tuning the qubit away from the driveline frequency of the rotation operation.

Abstract: A lighting device including a plurality of light-emitting semiconductor devices. The light-emitting semiconductor devices are separated into at least two subgroups. The lighting device further includes a plurality of optics separated into at least two subgroups, which are arranged relative to the plurality of light-emitting semiconductor devices such that each one of the plurality of light-emitting semiconductor devices of a first subgroup is located at a focal point of a respective optic of a first subgroup of the plurality of optics, and such that each one of the plurality of light-emitting semiconductor devices of a second subgroup is located at a focal point of a respective optic of a second subgroup of the plurality of optics. The optical properties of the first subgroup and second subgroup of the plurality of optics are different.

Abstract: In an embodiment, a quantum circuit (circuit) includes a first qubit and a second qubit. In an embodiment, a quantum circuit includes a tunable microwave resonator, wherein a first applied magnetic flux is configured to tune the microwave resonator to a first frequency, the first frequency configured to activate an interaction between the first qubit and the second qubit, and wherein a second applied magnetic flux is configured to tune the microwave resonator to a second frequency, the second frequency configured to minimize an interaction between the first qubit and the second qubit.

Abstract: A semiconductor building block is disclosed which includes a plurality of logic gates, each having at least one P-channel device, at least one N-channel device, and a current controller controlling current for each of the plurality of logic gate having a voltage source input (vdd), a ground input (vss), a first input current (ibiasn) adapted to control current through the at least one N-channel device, a second input current (ibiasp) adapted to control current through the at least one P-channel device, and an analog voltage input (delta) representing i) a predetermined ratio between respective on currents in the at least one P-channel device to ibiasp, and ii) the predetermined ratio between respective on currents in the at least one N-channel device to ibiasn.

Abstract: A load control device for controlling the amount of power delivered to an electrical load is able to operate in a normal mode and a burst mode. The load control device may comprise a control circuit that activates an inverter circuit during active state periods and deactivates the inverter circuit during inactive state periods. The control circuit may operate in the normal mode to regulate an average magnitude of a load current conducted through the electrical load to be above a minimum rated current. The control circuit may operate in the burst mode to adjust the average magnitude of the load current to be below the minimum rated current. The control circuit may adjust the average magnitude of the load current by adjusting the length of the inactive state periods while holding the length of the active state periods constant.

Abstract: A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

Abstract: A system and method comprising a cryogenic adiabatic circuit in a cryogenic environment and a clock generator at a higher temperature, the circuit's clock lines can be connected across the temperature gradient to the clock generator, where the clock generator runs below the frequency that would yield power dissipation equal to the static dissipation of a functionally equivalent CMOS circuit at room temperature, resulting in lower power for the function than possible at room temperature irrespective of the speed of operation.

Abstract: A computer system may include circuit blocks that may operate in different operating modes. When operating in a retention mode, a voltage level of a local power supply node for a particular circuit block may be less than a voltage level of the local power supply node when the particular circuit block is operating in an active mode. An output buffer circuit may be configured to generate, when the particular circuit block is operating in retention mode, an output signal using a circuit signal generated by the particular circuit block, and a voltage level corresponding to the active mode of operation.

Abstract: A quantum processing apparatus comprises control electronics, a switching unit, a bias line, and N electronic circuits. Both the switching unit and the bias line are connected to the control electronics. The N circuits comprise N respective, non-volatilely tunable resistors and N respective frequency-tunable, solid-state qubits. The control electronics are configured to individually tune the resistors via the switching unit, in a configuration mode of the apparatus; and apply a voltage bias to the electronic circuits via the bias line, in an operation mode of the apparatus. The electronic circuits are configured to passively apply respective bias signals to the qubits, wherein such bias signals are impacted by the resistors, in response to the voltage bias applied via the bias line, to operate the qubits at respective frequencies determined according to the respective bias signals.

Abstract: Pulsed radiation is generated at a power level that depends on a voltage level, frequency and duty cycle of a pulsed high voltage. A pulsing switch generates the pulsed high voltage from a high voltage and a pulse control signal. The pulsing switch has first and second bi-polar active switches connected in series between a high voltage conductor and a ground conductor. The pulsed high voltage is produced at a connection between the first and second bi-polar active switches when the first and second bi-polar active switches are repeatedly pulsed on and off to alternatingly connect the high voltage conductor and the ground conductor to a pulsed voltage output.

Abstract: An integrated circuit provides a semiconductor die with I/O bond pads, a power bond pad, and a circuit ground pad. Each I/O bond pad is associated with an input circuit that has an input circuit output lead. Sets of digital logic functional circuitry on the die provide different digital logic functions. Each function includes logic input leads and logic output leads. Output circuits each have an output circuit in lead and an output circuit out lead. Strapping structures, such as vias, formed in the semiconductor die electrically couple input circuits to a selected set of digital logic functions and the selected set of digital logic functions to output circuit in leads. Upper level metal conductors couple output circuit out leads and selected I/O bond pads.

Abstract: A non-volatile logic device for energy-efficient logic state restoration is disclosed. The non-volatile logic device incorporates a volatile flip-flop and a non-volatile storage unit to achieve on-chip non-volatile storage. The non-volatile logic device further allows for a backup time to be determined on a per-chip basis, resulting in minimizing energy wastage and satisfying a given yield constraint.

Abstract: A TFT substrate includes a gate metal layer including a gate electrode of a TFT and a patch electrode, a gate insulating layer formed on the gate metal layer and including a first opening at least reaching the patch electrode, a source metal layer formed on the gate insulating layer, and including a source electrode of the TFT, a drain electrode, and a drain extending section extending from the drain electrode, an interlayer insulating layer formed on the source metal layer, and including a second opening overlapping the first opening when viewed from a normal direction of a dielectric substrate and a third opening at least reaching the drain extending section, and a conductive layer formed on the interlayer insulating layer and including a patch drain connection section. The patch drain connection section is in contact with the patch electrode within the first opening and in contact with the drain extending section within the third opening.

Abstract: A closet lighting system incorporates a light strip that extends around an inside perimeter of a closet doorway and is configured to automatically turn on when motion is detected in the doorway. Motion may be a closet door opening or a person moving into a closet doorway, either walking into or reaching in. A closet lighting system has one or more activity sensors to detect the motion in the closet doorway. A first activity sensor may be configured proximal to the control system or the connected end of the light strip to the controller. A second activity sensor may be configured on a distal end of the light strip and may send a motion signal through the light strip, such as through a data line or through a power line. A motion signal may a voltage signal passed through the power line below a voltage to activate the lights.

Abstract: An assembly is provided for a transverse electromagnetic (TEM) system. The assembly includes a support frame and at least one resistive sheet. The support frame includes an upper plate and a lower plate. The upper plate defines a first inner surface and an opposed first outer surface. The lower plate defines a second inner surface and an opposed second outer surface. The at least one resistive sheet is coupled to at least one of the upper plate or the lower plate, and extends parallel to the upper plate and lower plate from an exterior of the support frame. The resistive sheet has an inner end disposed proximate the at least one of the upper plate or lower plate and an outer end disposed opposite the inner end, and has a variable resistance that is greater at the outer end than at the inner end.

Abstract: Provided is a hand-type low temperature microwave plasma generator that is configured to implement plasma even in a low power state, and be easily applied to various small devices using microwave plasma including medical treatment and the like of wound treatment or cell treatment.

Abstract: A CNOT gate includes a clock line, splitter, and first and second store-and-launch gates (SNLs) to each output a fluxon in accordance with a clock fluxon and polarities of an input fluxon and the clock fluxon. The CNOT gate also includes first and second IDSN gates. When one fluxon input is received, the IDSN gate outputs one fluxon in accordance with a polarity of the fluxon input. When two fluxon inputs are received, the IDSN gate outputs two fluxons in accordance with an inverse polarity of the fluxon inputs. The CNOT gate also includes first and second NOT gates to receive a fluxon output from the first IDSN gate and output a fluxon of opposite polarity, and a third NOT gate to receive a fluxon output from the second IDSN gate and output a fluxon of opposite polarity.