Abstract: A programmable logic device includes an array of logic modules. A standard interconnection grid, with vertical routing lines, horizontal routing lines, and local routing lines, links the array of logic modules. An omniversal bus is positioned over the array of logic modules. The array of logic modules includes selective links to the omniversal bus, such that the omniversal bus dynamically establishes autonomous sub-arrays of logic modules of variable size attached to the omniversal bus.

Abstract: PRS07010 A simplified implementation of molecular field programmable gate arrays described in U.S. Pat. No. 6,215,327, reducing the complexity of a single site in a tiled array template to that of a 2-input lookup table.

Abstract: This invention discloses a customizable and programmable integrated circuit device including at least first and second programmable logic cells, and at least two electrical conductive paths interconnecting the at least first and second programmable logic cells, at least a portion of which can be removed for customization of the integrated circuit device, wherein the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.

Abstract: A system and method is provided for providing optimal input and output impedances at a telecommunications interface. Input and output impedances can be adjusted manually, or the optimal impedance can be sensed and provided for automatically at the selected interface.

Abstract: A current driver, a common mode voltage monitoring circuit and a current compensator are provided to drive a twisted pair cable, which is made up of two signal lines coupled to a terminal bias voltage through respective terminal resistors. The common mode voltage monitoring circuit monitors a difference between a common mode voltage of the twisted pair cable and a supply voltage level for the current driver. And the current compensator is coupled to the twisted pair cable to compensate for an output current of the current driver in accordance with a result of monitoring performed by the common mode voltage monitoring circuit. If the current driver has decreased its current drivability due to a drop of the supply voltage level of the current driver or a variation in the common mode voltage of the twisted pair cable, then the current compensator compensates for the decrease. Thus, the current driver can continuously operate in a broad voltage range to supply a constant current.

Abstract: An impedance matching arrangement, including an adaptive circuit. The adaptive circuit includes a first adaptive portion allowing impedance matching according to a predetermined first weighting scheme, and a second adaptive portion allowing impedance matching according to a predetermined second weighting scheme which differs from the first weighting scheme. The first adaptive portion is operable substantially during initialization times, and the second adaptive portion is operable substantially outside initialization times. The first adaptive portion may have a binary weighting scheme, and the second adaptive portion may have a linear weighting scheme. Finally, the adaptive 1 circuit is provided as a portion of an integrated circuit (IC) die.

Abstract: A method and apparatus for enhancing noise tolerance in dynamic Silicon-On-Insulator (SOI) logic gates improves the performance of dynamic gates using SOI technology. In particular implementations of logic, the logic inputs can be used to enable a pull-up chain constructed from a plurality of transistors. This pull-up chain holds the preset voltage on the summing node of the dynamic logic gate while the logic inputs are in a combination where parasitic bipolar transistors in the input logic chains conduct. The pull-up chain prevents spurious operation of the logic gate due to the conduction of the parasitic bipolar transistors. The pull-up also prevents spurious operation due to charge sharing that occurs when a device in the logic chain is enabled while another device is disabled. The charge sharing occurs due to charging the diffusion capacitance of the device which is disabled.

Abstract: Disclosed are output drivers for integrated circuit chips which receive a second supply voltage VCCQ for driving signals off the chips. The output drivers according to the present invention can accept a wide range of voltage values for the second supply voltage VCCQ, and control their rise and fall slew times so that there is only a small variation in the slew times over a wide range of VCCQ values. The charging and discharging of the driver's pull-up and pull-down transistors is varied as a function of the second supply voltage VCCQ. In one set of embodiments, constructive discharge current branches and charging current branches are selectively activated depending upon the value of VCCQ. In other embodiments, counteracting discharge current branches and charging current branches are selectively activated depending upon the value of VCCQ.

Abstract: A hierarchy of multiplexers is provided to generate functions of more inputs than the lookup table can handle. For example, a lookup table having 16 memory cells can generate functions of four input signals. By combining the outputs of two lookup tables in a multiplexer (F5) controlled by a fifth input signal, any function of five input signals can be generated. Using a sixth signal to select between the outputs of two such F5 multiplexers allows any function of six input signals to be generated, and so forth. In one embodiment, a configurable logic block (CLB) includes four slices, each having two four-input lookup tables (a total of eight lookup tables). The multiplexer hierarchy allows for all functions of eight input signals to be generated by selecting the output signal of one of the 16 lookup tables in a pair of CLBs.

Abstract: An interface circuit functions as a so-called voltage tolerant circuit to which signals may be applied from, for example, a 3.3-V internal source or from an external source operating with a supply voltage greater than the internal source, for example, a 5-V source. By eliminating a floating voltage state in the internal circuits, problem-causing current leaks can be prevented in substantially all operating modes, that is, in any signal input or output mode, and in any voltage transition state, that is, irrespective of the sequence in which, for example, 0-V, 3.3-V, and 5-V signals are applied.

Abstract: A telephone line feed circuit for use with a telecommunication line has dual drivers with differing ratio transformer taps and a sensing circuit so that under normal drive conditions a first driver supplies substantially all power through a first transformer of a first turns ratio under normal in put signal conditions and a second driver supplies substantially all power through a second transformer of a second turns ratio under high crest factor input signal conditions.

Abstract: A system includes a transmission line, a driver, a load, a compensation capacitor and a compensation resistor. An output terminal of the driver is coupled to one end of the transmission line, and the load is coupled to the other end of the transmission line. The compensation capacitor is coupled in parallel with the output terminal of the driver, and the compensation resistor is coupled in series between the other end of the transmission line and the load.

Abstract: A programmable logic device has plural regions of programmable logic and a general-purpose interconnection network for conveying signals to, from, and between the regions. In addition to the general-purpose interconnection network, more direct interconnections are provided from outputs of each region to inputs of one or more other adjacent or nearby regions. At least some of these direct interconnections are preferably multiplexed with more conventional inputs to the other regions so that the input resources required for each region do not become excessive. The invention is particularly useful for devices which perform basic logic using sum-of-products (“Pterm”) logic. However, the invention is also useful in other types of devices such as those which perform basic logic using look-up tables.

Abstract: A circuit for converting a negative ECL level to a positive CMOS level is formed by a level conversion circuit input terminal 4 for inputting a negative ECL level, a level shifter 5, one end of which is connected to the input terminal 4, a load 6 of the level shifter 5, one end of which is connected to the level shifter 5 and the other end of which is connected to a positive power supply VDD, and a positive ECL-CMOS level converter 7 for comparing a voltage that is level shifted by the level shifter 5 with a reference voltage Vref and converting to a CMOS level.

Abstract: The present invention provides a method and system for a contention prevention scheme which provides contention prevention during scan-based test without adversely affecting the functional timing of the path circuit. The contention prevention scheme provides a circuit which includes a path circuit gated by a contention prevention circuit (CPC) and the CPC, where the CPC allows functional operation to occur without adversely affecting the functional operation timing, provided that a time skew between two input signals to the CPC is approximately less than a difference between a time delay associated with a scan-based test logic value and a time delay associated with a functional logic value. With a contention prevention circuit tuned in this manner, a static logical value during functional mode is provided, indicating no contention, which avoids adversely affecting the functional timing of the path circuit.

Abstract: A high-level signal is sent to a mode control terminal, a pulse for slew-rate adjustment is sent to a replicated gate, and the slew rate at a measurement terminal is set to a desired value using a switch unit. The slew rate of the replicated gate having the same structure as the structure of output circuits and being formed on the same semiconductor substrate is set based on digital signal which are generated upon operation of the switch unit. The slew rate of output circuits is so adjusted as to be the same as the slew rate of the replicated gate.

Abstract: A CMOS input/output control circuit capable of operating normally under different input voltages such as 2.5 V, 3.3 V and 5 V. Moreover, the PMOS transistor inside the n-well region is shut by a gate control circuit and an n-well control circuit of this invention when a 5 V input voltage is applied to the circuit.

Abstract: A self-timed pipelined datapath system reduces its power dissipation by accurately controlling the active and inactive states of the multi-threshold CMOS (MT-CMOS) circuit used as its combinational circuit. The MT-CMOS circuit comprises a logic circuit of low-threshold and a power control circuit formed of high-threshold transistors for controlling the power feeding to the logic circuit. The self-timed pipelined datapath system comprises: a pipelined datapath circuit including a plurality of data processing stages, each having a combinational circuit for processing input data and a register connected to the input side of the combinational circuit; and an asynchronous signal control circuit that controls data transmission to and from each of the registers in the pipelined datapath circuit in response to a request signal.

Abstract: An input buffer capable of high voltage operation includes a transmission gate connected to a boosting voltage source. The input buffer can be used to maintain the processing speed and noise margin of a digital circuit even through the input voltage thereof is excessively high. Moreover, the input buffer can be used in an address latch or inverter-type circuit.

Abstract: A high-voltage level tolerant transistor circuit, comprising a plurality of cascoded transistors, including a first transistor (T1) operatively connected to a high-voltage level node (3) and a second transistor (T2) operatively connected to a low-voltage level node (2). The first transistor (T1) connects to a biasing circuit (8), such as a voltage level shifter, providing a variable biasing level (V1) relative to a voltage level (VH) at the high-voltage level node (3).