Abstract: A device layout is disclosed for an ESD device for protecting NMOS or Drain-Extended (DENMOS) high power transistors where the protection device (an SCR) and the NMOS or DENMOS transistors are integrated saving on silicon real estate. The integration is made possible by adding a p.sup.+ diffusion to the n-well (drain) of a high power NMOS (DENMOS) transistor such that the added p.sup.+ diffusion together with the aforementioned n-well and the p-substrate of the silicon wafer create one of the two transistors of the SCR. A low triggering voltage of the SCR is achieved by having the second parasitic npn transistor of the SCR in parallel with the NMOS (DENMOS) transistor by sharing the n-well (collector/drain), p-substrate (base/channel region), and an adjacent n.sup.+ diffusion (emitter/source) in the p-substrate. A high HBM ESD Passing Voltage is obtained by utilizing the tank oxide method of a DENMOS transistor.

Abstract: In a method of manufacturing a semiconductor device, an insulating film having an opening is formed on an amorphous film 103 containing silicon therein. After catalytic elements are introduced from the opening, the amorphous film 103 is crystallized. Thereafter elements (phosphorus) selected from Group XV are introduced from the opening, and then a heat treatment is conducted to obtain a film having crystallinity. Thereafter, a portion of the film containing silicon into which the catalytic elements and phosphorus is introduced are removed.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a trench for isolating an element region on a semiconductor substrate, burying a first oxide film in the trench so as to contact a surface of the trench, flattening a surface of the first oxide film, heating the semiconductor substrate to form a second oxide film at an interface between the surface of the trench and the first oxide film, and annealing the semiconductor substrate.

Abstract: The present invention is directed to a packaged semiconductor chip that utilizes a multilevel leadframe that positions the lead fingers close to the bond pads while positioning the bus bars on a different level and behind or outboard of the lead finger connections such that it is unnecessary for any wires to cross over the bus bars or the lead fingers. The leadframe may comprise a multi-part frame, or be fabricated from a single sheet of metal.

Abstract: A semiconductor processing method of forming complementary metal oxide semiconductor memory circuitry includes, a) defining a memory array area and a peripheral area on a bulk semiconductor substrate, the peripheral area including a p-well area for formation of NMOS peripheral circuitry, the peripheral area including a first n-well area and a second n-well area for formation of respective PMOS peripheral circuitry, the first and second n-well areas being separate from one another and having respective peripheries; b) providing a patterned masking layer over the substrate relative to the peripheral first and second n-wells, the masking layer including a first masking block overlying the first n-well and a second masking block overlying the second a-well, the first masking block masking a lateral edge of the first n-well periphery; and c) with the first and second masking blocks in place, providing a buried n-type electron collector layer by ion implanting into the bulk substrate; the resultant n-type electron

Abstract: A semiconductor device having gate electrodes with different gate insulators and a process for fabricating such device is provided. Consistent with one embodiment of the invention, a semiconductor device is provided in which a first gate insulator is formed over a first region of a substrate. A second gate insulator, different than the first gate insulator, is formed over a second region of the substrate. Finally, one or more gate electrodes are formed over each of the first and second gate insulators. The first gate insulator may, for example, have a permittivity and/or a thickness which is different from that of the second gate insulator. For example, the first gate insulator may have a permittivity greater than 20, and the second gate insulator may have a permittivity less than 10.

Abstract: The present invention includes patterning a metal layer on a glass substrate. A dielectric layer is formed on the metal layer. An amorphous silicon layer is subsequently formed on the dielectric layer. A first positive photoresist is formed on the amorphous silicon layer. Then, a back-side exposure is used by using the gate electrodes as a mask. A bake step is performed to expand the lower portion of the photoresist. Next, a second positive photoresist layer is formed on the amorphous silicon layer and the residual first positive photoresist layer. A further back-side exposure is employed again from the back side of the substrate using the gate electrode as the mask. A second back step is applied to expand the lower portion of the second positive photoresist layer. An ion implantation is performed by using the second positive photoresist as a mask. Next, the substrate is then annealed. Amorphous silicon layer is then patterned.

Abstract: A semiconductor memory device has word line conductor films, bit line conductor films transverse to the word line conductor films and memory cells provided at intersections between the word line conductor films and bit line conductor films. Each memory cell has a transistor structure formed at a surface portion of a semiconductor substrate and a capacitor structure formed over the semiconductor substrate. The word line conductor films are formed at a level lower than the capacitor structures of the memory cells to improve the resolution of patterns for the semiconductor memory device.

Abstract: Within an integrated circuit, a contact plug with a height not extending above the level of the gate/wordline nitride is nonetheless provided with a relatively large contact area or landing pad, significantly larger than the source/drain region to which the contact plug is electrically connected. Methods for producing the inventive contact plug include (1) use of a nitride facet etch, either (a) during a nitride spacer formation etch or (b) during a BPSG etch; (2) using at least one of (a) an isotropic photoresist etch or partial descum to narrow BPSG spacers above the gate/wordline nitride, and (b) a nitride step etch to etch the shoulder area of the gate/wordline nitride exposed by a BPSG etch; and (3) polishing a BPSG layer down to the top of a gate/wordline nitride before any doped polysilicon plug fill, masking for BPSG etch and performing a BPSG etch, etching the photoresist layer through a partial descum, and etching the shoulder area of the gate/wordline nitride exposed thereby.

Abstract: A semiconductor integrated circuit (IC) device has a silicon-on-insulator substrate having a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a silicon layer formed on the insulating film. The semiconductor IC device includes at least one semiconductor device formed on the semiconductor substrate, and at least one semiconductor device formed on the silicon layer and operated with a power-supply voltage different from a power-supply voltage for the semiconductor device formed on the semiconductor substrate.

Abstract: An electronic package is made by electrically bonding groups of conductive leads to two circuitized members after aligning the leads with electrical conductors on the circuitized members. Retention members may be used to hold the leads in alignment relative to each other prior to bonding and then are removed. Removal may include tearing away the retention member in propinquity to notches in the leads.

Abstract: A semiconductor device includes a semiconductor chip in which electrode pads are formed with a first pitch, leads electrically connected with the electrode pads through lines, and sealing plastic sealing the semiconductor chip. In the semiconductor device, projections used for external connection ports are formed in the leads with a second pitch. The sealing plastic seals the lines connecting the electrode pads and the leads, but the projections are exposed from the sealing plastic.

Abstract: Fluorine bearing spacers on the sidewalls of gate electrodes of a semiconductor device are provided to suppress hot carrier injection in the semiconductor device. In accordance with one embodiment of the invention, a semiconductor device is formed by forming at least one gate electrode on a surface of a substrate and forming fluorine bearing spacers on the sidewalls of the gate electrode. The fluorine bearing spacers may, for example, be formed of an NF.sub.3 -doped glass material.

Abstract: An electrostatic discharge (ESD) protection circuit includes diodes connected in series back-to-back between the signal input and power supply terminals of the circuit to be protected. This allows the input signal to rise a selected distance above the supply voltage without triggering the ESD protection circuit. The ESD protection circuit can be fabricated in integrated form, with the diodes including a pair of P+ regions in an N-well or separate P+ regions forming PN junctions with separate N-wells. The diodes may also be formed in a layer of polysilicon over a field oxide region. Optionally, a second pair of back-to-back diodes can be connected between the signal input terminal and ground. This permits the input signal to fall a selected distance below ground without triggering the ESD protection circuit.

Abstract: An ETOX cell that has improved injection of electrons from a forward biased deep n-well to p-well junction underneath the channel area of a triple-well ETOX cell during substrate hot electron (SHE) programming. The ETOX cell has a control gate, a floating gate, a deep n-well formed in the substrate, a buried n+ layer in the deep n-well, a p-well formed in the n-well and atop the buried n+ layer, a drain implant formed in the p-well, and a source implant formed in the p-well. The buried n+ layer enhances the parasitic bipolar action between the n+ source/drain (as collector), the p-well (as base), and the buried n+ layer (as emitter). The parasitic transistor amplifies the amount of seed electrons injected into the p-well, which in turn results in significantly faster programming of the ETOX cell.

Abstract: Heterojunction bipolar transistors (130) with bases (138) including an etch stop element are disclosed. The preferred embodiment devices have Al.sub.x Ga.sub.1-x As emitters (140) and GaAs collectors (136) and bases (138) with In.sub.y Ga.sub.1-x As added to the bases (138) to stop chloride plasma etches.

Abstract: A method and apparatus for a reinforced leadframe to substrate attachment in a semiconductor assembly. In one embodiment, a printed circuit board having a plurality of electrically coupled electrical contact regions and wire bond areas formed thereon has a leadframe attached thereto such that each of the bonding fingers of the leadframe is coupled to a respective electrical contact region on the printed circuit board. A ribbon of B-staged epoxy is disposed on the leadframe such that said leadframe is disposed between the ribbon of B-staged epoxy and the printed circuit board. An integrated-circuit die is mounted on the printed circuit board with the bonding fingers of the leadframe peripherally surrounding the integrated circuit die. The bonding pads on the integrated-circuit die are electrically coupled to respective wire bond areas on the printed circuit board.

Abstract: A transistor structure for an ESD protection device, which includes a gate structure constituted by a connecting part and a plurality of protecting parts on a substrate. The protecting parts include a first protecting part and a second protecting part, wherein the first protecting part is located closer to the middle of the gate structure and the second protecting part is located further from the middle of the gate structure. The width of the second protecting part is larger than that of the first protecting part. There are sources and drains alternated with the protecting parts, wherein the sources include a first isolated from the drain by the first protecting part and a second source isolated from the drain by the second protecting part. The substrate junction is connected to the second source with a butting face and a butting contact is located above the butting face to connect the second source and the substrate junction simultaneously.

Abstract: A stress-free wafer comprising a substrate formed of a semiconductor material having front side and back side planar and parallel surfaces and having a thickness ranging from 2 to 7 mils. The front side has electronic circuitry therein with exposed contact pads. The back side is ground and polished so that the wafer is substantially stress free and can withstand bending over a 2" radius without breaking or damaging.

Abstract: A semiconductor device having a structure including no LDD region while being structured in such a manner that fixed charges are charged in portions of a gate oxide film overlapping with side walls of a gate electrode formed on the gate oxide film so as to reduce the intensity of electric field between the source and drain of a transistor included in the semiconductor device. The charged-up positive or negative fixed charges serve to invert the conductivity of the channel region portion of a semiconductor substrate on which the gate oxide film is formed, thereby providing the same effect as the LDD region. The invention also provides a method for fabricating the semiconductor device.