Abstract: A transistor (100) having a strip channel or channels (108) in which the current flow in is the lateral direction between source (110) and drain (112). The gate (116) is located on the sidewalls and, if desired, the top of the strip channel (108). In a preferred embodiment of the invention, a disposable gate process is used that allows the source (110) and drain (112) regions to be self-aligned to the gate (116).

Abstract: A static random access memory (SRAM) device having an improved degree of integration. The SRAM device has a cell array region in which a unit cell is arranged in a matrix. The unit cell includes a first NMOS inverter including a first NMOS driver transistor and a first NMOS access transistor, a second NMOS inverter including a second NMOS driver transistor and a second NMOS access transistor, a first CMOS inverter including the first NMOS driver transistor and a first PMOS load transistor, and a second CMOS inverter including the second NMOS driver transistor and a second PMOS load transistor, wherein the first and second NMOS inverters, and the first and second CMOS inverters are respectively connected by a flip-flop, and a pick-up region for applying a predetermined bias voltage to the memory cell array region formed in a semiconductor substrate is included in the memory cell array region.

Abstract: Two wafers are bonded together through an annealing process that maintains temperatures at CMOS compatible levels (i.e., below 500 degrees Celsius). A layer of palladium (Pd) is formed on a first wafer. Preferably an adhesion layer of chromium (Cr) attaches the palladium layer to the first wafer. The palladium layer is engaged with silicon (Si) from a second wafer, and the engaged wafers are annealed to form a palladium-silicide (PdSi) bond between the palladium layer of the first wafer and the silicon of the second wafer. In addition to bonding the first wafer to the second wafer, the palladium-silicon bond may be used to form an electrical connection between the two wafers so that circuits on both wafers may communicate to one another through the palladium-silicon bond.

Abstract: A metal feature, defined by gaps in a patterned metal layer, is formed with an inwardly tapering profile so that it is wider at the top than at the bottom. The metal feature advantageously presents a larger landing area for vias while maintaining the dimensions and intraline coupling capacitance requited by design. The gaps in the patterned metal layer can be filled with a spin-on dielectric material such as spin-on glass (SOG) or hydrogen silsesquioxane (HSQ).

Abstract: A system and method for using a nitrous oxide plasma treatment to eliminate defects at an interface between a stop layer and an integral layered dielectric. The system and method provide a reliable and simplified technology that eliminates the small bubble-like defects that can be common to thin nitride layers. The system includes a plasma device and a processing chamber. The method encompasses the steps of preparing a first integral layered dielectric on a substrate before depositing a stop layer thereupon. A plasma gas is then ionized. Preferably, the plasma gas is composed of nitrogen and oxygen. The stop layer is then exposed to the plasma gas until a primary surface of the stop layer is bombarded plane. A second integral layered dielectric is then formed on the primary surface. A top surface of the second integral layered dielectric is generally plane and parallel to the primary surface.

Abstract: A double-crown rugged polysilicon capacitor of a dynamic random access memory cell is formed. A second dielectric layer is formed on a first dielectric layer, followed by the formation of a first conductive layer on the second dielectric layer. Portions of the first conductive layer and the second dielectric layer are removed to define an opening. A second conductive layer is formed within the opening and on the first conductive layer. A sidewall structure is formed within the opening on sidewalls of the second conductive layer. Next, a removing step is performed to remove a portion of the second conductive layer which is uncovered by the sidewall structure. The sidewall structure and a portion of the first dielectric layer are removed, using the residual second conductive layer as a mask, to define a contact hole within the first dielectric layer. A third conductive layer fills up the contact hole.

Abstract: A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.

Abstract: A solder paste brick, for attaching a ball grid array device to a circuit board. The solder paste brick is configured as an irregularly shaped structure so as to reduce distances in which volatized flux gasses must travel in order to escape from within the solder paste brick, thereby reducing voiding in a solder joint formed by the solder paste brick and a solder ball terminal of the ball grid array device as a result of a reflow soldering process. The solder paste brick is further configured so as to allow the solder ball terminal to make contact with a portion of an edge of the solder paste brick, while remaining substantially aligned with a center of a pad of the circuit board, such that a majority of a top surface of the solder paste brick is not in contact with the solder ball terminal. In this way, volatized flux gases formed during a reflow soldering process are caused to escape via the top surface without migrating upwardly into the solder ball terminal during the reflow soldering process.

Abstract: A semiconductor package provided with a reinforcing plate on the side of the lead joined face of which a chip housing concave portion is formed, a semiconductor chip housed and fixed in the chip housing concave portion of this reinforcing plate, a plurality of leads joined and held on the lead joined face of the reinforcing plate, the inner lead section of which is joined to the semiconductor chip via a bump and in the outer lead section of which a protruded electrode is formed, a solder resist film formed on the lead except the bump formed area and the electrode formed area of this lead and a polyimide film formed on the side of the inner lead section of the lead on the solder resist film and the manufacturing method are disclosed and hereby, the quality of the semiconductor package with ultra-multipin structure is stabilized.

Abstract: A method for manufacturing a memory device having a plurality of memory cells. Each memory cell has a non-volatile resistive memory element with a small active area. A plurality of memory cells are formed at selected locations of at least a portion of a semiconductor wafer. To form the memory cells, a lower electrode layer and a memory material layer are deposited over at least a portion of the wafer. Patterns are formed over desired contact locations of the memory material layer and etching is used to remove portions of the memory material layer. The etching step undercuts the patterns and forms memory elements having a protruding contact portion with an apex contact area. The pattern is removed, and an upper electrode is formed and electrically coupled to the contact area. Corresponding access devices and word/bit line conductor grids are provided and coupled to the memory cells.

Abstract: A tub structure underlying a first well in a semiconductor integrated circuit is charge pumped to increase electron collection efficiency in the tub structure. A charge pumping circuit applies the biasing voltage via a second well. The current in the tub structure is monitored to determine when to pump charge into the tub structure. The pumping biases the n-tub to voltages as high as twice the supply voltage magnitude, (2V.sub.cc). The tub current is compared to a minimum current threshold and a maximum current threshold. The charge pump is disabled when the tub current exceeds the maximum threshold and is turned on before the tub current goes below the minimum threshold. The maximum threshold is for keeping the tub structure from exhibiting an undesirable standby current. The minimum threshold is to keep the tub structure biased enough to achieve a desired electron collection efficiency.

Abstract: A variable capacitor in a semiconductor device is described in which the capacitance is varied by the movement of a dielectric material in the space between the plates of the capacitor in response to an external stimulus. A method of making such a variable capacitor is also described in which the capacitor is built in a layered structure with the top layer including a portion of dielectric material extending into the space between the capacitor plates. After formation of the top layer, an intermediate layer is etched away to render the top layer flexible to facilitate movement of the dielectric material in the space between the capacitor plates.

Abstract: A method is described for fabricating a module having a chip attached to a carrier substrate, wherein a guide substrate transparent to ablation radiation is used. A removable layer is provided on a surface of the guide substrate. A first alignment guide is formed on the removable layer, and a second alignment guide is formed on a front surface of the chip. The chip is aligned to the guide substrate by contacting the second alignment guide to the first alignment guide; the chip is then attached to the guide substrate. The carrier substrate is attached to the chip at the back surface of the chip. The interface between the removable layer and the guide substrate is then ablated using radiation (typically laser radiation) transmitted through the guide substrate, thereby detaching the guide substrate. Thin films with metal interconnections may then be provided on the front surface of the chip.

Abstract: A plastic encapsulated integrated circuit package is disclosed which comprises a multilayer ground plane assembly bonded to a lead frame with an integrated circuit die bonded to the composite assembly. The multilayer ground plane assembly is first formed by bonding together a metal sheet, such as a copper sheet, and a thermally conductive insulating layer, such as a thermally conductive polyimide material, to which is also bonded a layer of a b-stage adhesive material. The ground plane assembly may be bonded to the lead frame by placing the b-stage adhesive layer of the ground plane assembly against the lead frame and heating the ground plane assembly and lead frame to a temperature of from about 120.degree. C. to just under 200.degree. C. for a time period not exceeding about 10 seconds to bond the b-stage adhesive layer to the lead frame without oxidizing the lead frame.

Abstract: An ink replenishment kit and method for an inkjet printer includes a replaceable ink supply module providing replenishment of an inkjet printhead. The module includes a collapsible bag, an enclosure box, a connective tube, and an on/off valve. These four components are incorporated into a composite sealed system which remains intact during shipment, storage, installation and operation. A coupler is provided to securely attach a print cartridge inlet with the on/off valve to hold them together in an open position allowing ink to be replenished into the print cartridge from the collapsible bag.

Abstract: It is intended to provide a semiconductor device and its manufacturing method in which a high-resistance region maintaining a high resistance even under high temperatures can be made in a nitride III-V compound semiconductor layer having an electric conductivity by ion implantation. After a nitride III-V compound semiconductor layer having an electric conductivity is grown, a high resistance region is formed in the nitride III-V compound semiconductor layer by locally implanting boron ions therein. The amount of implanted boron is preferably not less than 1/30, or more preferably not less than 1/15, of the carrier concentration of the nitride III-V compound semiconductor layer. The high-resistance region is used as a device isolating region of an electron moving device or as a current blocking layer of a semiconductor laser.

Abstract: A semiconductor device and a fabrication method therefor improve electrostatic discharge (ESD) protecting property of an ESD protecting device in a fabrication method of a semiconductor device using a self-aligned silicide CMOS process. The semiconductor device has a silicide blocking portion which prevents a self-aligned silicified reaction by forming a gate electrode on drain and/or source of an ESD protecting device and simultaneously forming a dummy gate electrode which is separated from the gate electrode.

Abstract: A semiconductor device include: a substrate of a conductivity type; a first well provided in the substrate and of the same conductivity type as the conductivity type of the substrate; a second well provided in the substrate and of an opposite conductivity type to the conductivity type of the substrate; and a buried well provided at a deep position in the substrate and of the opposite conductivity type to the conductivity type of the substrate. A buried well of the same conductivity type as the conductivity type of the substrate is further provided so as to be in contact with at least a part of a bottom portion of the first well so that the first well is at least partially electrically connected to the substrate.

Abstract: A multi-step dry-etching method that sequentially employs plasma etching and reactive ion etching process steps to form the pairs of adjacent, doped polysilicon gate electrodes of a twin-well CMOS device. The initial dry-etching process step uses to best advantage the speed of plasma etching to rapidly form pairs of adjacent p- and n-type gate-precursor features with substantially vertical sidewalls from the upper 50-80% of a doped polysilicon layer which lies on an insulating film. The gate-precursor features and, subsequently, the gate electrodes are formed from pairs of adjacent p- and n-type regions within the doped polysilicon layer which lie over pairs of adjacent n- and p-wells (the twin wells of the CMOS device), respectively, within a substrate. The subsequent dry-etching process step uses reactive ion etching to complete the formation of the pairs of adjacent, doped polysilicon gate electrodes from the remaining 50-20% of the etched, doped polysilicon layer without over-etching the insulating film.

Abstract: The present invention includes forming a gate on a transparent substrate. A gate isolation layer is then formed on the gate. An amorphous silicon (a-Si) layer and n+ doped silicon layer are successively formed on the gate isolation layer. Then, the a-Si layer and the n+ doped silicon layer are patterned. A first, a second and a third metal layers are successively formed on the n+ doped silicon layer, thereby forming a multi-metal layer structure. Subsequently, a wet and a dry etching is utilized to etch the multi-metal layer, thereby defining the S/D electrodes. A passivation layer is deposited on the S/D structure.