Abstract: A sensor having high sensitivity is formed using a suspended structure with a high-density tungsten core. To manufacture it, a sacrificial layer of silicon oxide, a polycrystal silicon layer, a tungsten layer and a silicon carbide layer are deposited in succession over a single crystal silicon body. The suspended structure is defined by selectively removing the silicon carbide, tungsten and polycrystal silicon layers. Then spacers of silicon carbide are formed which cover the uncovered ends of the tungsten layer, and the sacrificial layer is then removed.

Abstract: The capacitor of the present invention mainly includes the storage node 52, the capacitor dielectric layer 54, and the conductive layer 56. The storage node 52 is formed on the semiconductor substrate 30, and the storage node 52 includes a base member 52a, two vertical members 52b, two horizontal members 52c, and two sidewall members 52d, in which the base member 52a provides a conductive communication to an underlying conductive region in the substrate 30, the two vertical members 52b respectively extends upward from two lateral ends of the base member 52a, the two horizontal members 52c respectively and outwardly extends from two top ends of the two vertical members 52b, and the two sidewall members 52d respectively and upwardly extending from two outward ends of said two horizontal members 52c. The dielectric layer 54 is covered on the storage node 52 and the conductive layer 56 is formed on the dielectric layer 54.

Abstract: A conductive plastic lead frame and method of manufacturing same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: The present invention provides a method of simultaneously forming a photo diode and a CMOS transistor on a semiconductor wafer. The surface of the semiconductor wafer comprising a P-type substrate with at least one N-channel MOS area for forming a NMOS transistor of the CMOS transistor, and a photo sensing area for forming the photo diode. The method employs a first ion implantation process to form a P-type well in the NMOS area. Next, a second ion implantation process simultaneously forms a first N-type doped area in a predetermined area of the photo sensing area and a lightly doped drain of the NMOS transistor on the surface of the P-type well of the N-channel MOS area. Finally, a third ion implantation process forms a second N-type doped area in part of the surface of the photo sensing area, and forms the source and drain of the NMOS in the P-type well of the NMOS. The second N-type doped area and the first N-type doped area of the photo sensing area are at least partially overlapping.

Abstract: In the preferred embodiment for forming a rugged polysilicon cup-shaped capacitor of a dynamic random access memory cell, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed on the first dielectric layer, followed by the formation of a first conductive layer on the second dielectric layer. Portions of the first conductive layer and the second dielectric layer are then removed to define an opening therein. A second conductive layer is formed conformably on the substrate within the opening and on the first conductive layer. A sidewall structure is then formed within the opening on sidewalls of the second conductive layer. Next, a removing step is performed to remove a portion of the second conductive layer which is uncovered by the sidewall structure. The sidewall structure and a portion of the first dielectric layer are removed, using the residual second conductive layer as a mask, to define a contact hole within the first dielectric layer.

Abstract: A semiconductor device mount structure containing a semiconductor device (10), a connection substrate (30) disposed at the lower side of the semiconductor device (10), and leads (20) which are connected to external connection terminals (12) of the semiconductor device (10) at one ends thereof, turned back and connected to wires provided on the connection substrate (30) at the other ends thereof. The connection substrate (30) is constructed by plural carrier substrates. Each of the plural carrier substrates is right-angled isosceles triangular, and the plural carrier substrates are arranged so as to form a substantially square shape at the lower portion of the semiconductor device (10).

Abstract: A process for manufacturing semiconductor packages comprising, respectively, a substrate, a chip which forms an integrated circuit and is attached to one region of the substrate, electrical connection means connecting the chip to a group of external electrical connection regions lying on one face of the substrate, as well as an encapsulation encasement. The process consists in producing, in a matrix configuration, a multiplicity of groups of connection regions (104a) on a common substrate plate (102), corresponding to as many chip attachment regions (109), in attaching a chip (103) to each attachment region (109) of the common substrate plate, in electrically connecting each chip (103) to the associated electrical connection regions (104a), so as to obtain an assembly (111) consisting of the substrate plate and the connected chips.

Abstract: A method of forming a vertical transistor memory device includes the following steps. Before forming the trenches, FOX regions are formed between the rows. Form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thick floating gate layer of doped polysilicon over the tunnel oxide layer filling the trenches and extending above the trenches. Etch the floating gate layer down below the top of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thick control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes.

Abstract: The present invention is an antifuse structure comprising an insulation layer between a top conductor and a bottom conductor. The insulation layer has a via. A resistive layer is adjacent the via and a plug is adjacent the resistive layer. The plug is in the via and is also adjacent the top conductor.The present invention also provides a method for fabricating the antifuse on a base. A bottom conductor is deposited on the base. An insulation layer are deposited adjacent the bottom conductor. An antifuse via is etched into the insulation layer. A resistive layer is deposited in the antifuse via. A plug is deposited. The plug extends into the antifuse via. A top conductor is deposited and patterned adjacent the plug.

Abstract: A semiconductor structure uses a shallow trench isolation (STI) region to realize a capacitor trench of a reduced size. Consistent with one embodiment of fabricating a memory cell, the invention includes selectively removing portions of a substrate using a patterned mask to form a capacitor trench and an isolation trench at least partially around the capacitor trench. An oxide is formed in the isolation trench and the capacitor trench and the oxide so selectively removed in the capacitor trench. Portions of the substrate defining the base and sidewalls of the capacitor trench are then doped and a capacitor dielectric is formed in the capacitor trench, leaving a portion of the trench unfilled. A polysilicon layer is formed it the unfilled portion of the capacitor trench and over the capacitor dielectric to form a plate of the storage capacitor.

Abstract: A stacked-type semiconductor chip package of a lead on chip structure which is modified for stacking chips in the package, including a plurality of leads each having an inner lead portion and an outer lead portion extending from the inner lead portion, a lower semiconductor chip having a plurality of center pads and disposed under the inner lead portion, an upper semiconductor chip having a plurality of side pads and disposed above the inner lead portions, a plurality of side adhesive insulating members inserted between the inner lead portions and each of the upper and lower semiconductor chips, a plurality of wires which provide electrical connection between the pads and the inner lead portions, and a molding body which seals the structure other than the outer lead portions.

Abstract: An embodiment of the instant invention is a method of making a semiconductor device situated within a package with conductive leads extending from the package, the method comprising the steps of: testing a plurality of the semiconductor devices so as to determine defective devices; and marking the defective devices with a polymer marker able to withstand temperatures in excess of 200 C., acids with a pH of less than 2, and basic solutions with a pH of greater than 11. Preferably, the polymer marker is comprised of a surfactant, a solvent, a polymer backbone, and a dye, and may additionally include an adhesion promoter. The surfactant is, preferably, comprised of: SVC-15, isopropanol, and any combination thereof. The solvent is, preferably, comprised of a substance consisting of: ENSOLV, bromopropane, chloropropane, and C.sub.n H.sub.2n+1 X (where X is a halogen and n is between 3 and 5), and any combination thereof.

Abstract: An array of DRAM cells having Y-shaped multi-fin stacked capacitors with increased capacitance is achieved. A planar first insulating layer is formed over the semi-conductor devices on the substrate. Polycide bit lines are formed on the first insulating layer, and a second insulating layer and a silicon nitride (Si.sub.3 N.sub.4) etch-stop layer are conformally deposited. A multilayer, composed of a alternating insulating and polysilicon layers, is conformally deposited over the bit lines. Capacitor node contact openings are etched in the multilayer and in the underlying layers to the substrate. A fourth polysilicon layer is deposited sufficiently thick to fill the node contact openings and to form the node contacts. The multilayer is then patterned to leave portions over the node contacts, and an isotropic etch is used to remove the insulating layers exposed in the sidewalls of the patterned multilayer to provide Y-shaped multi-fin capacitor bottom electrodes over the bit lines.

Abstract: Metal semiconductor nitride gate electrodes (40, 70) are formed for use in a semiconductor device (60). The gate electrodes (40, 70) may be formed by sputter deposition, low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD). The materials are expected to etch similar to silicon-containing compounds and may be etched in traditional halide-based etching chemistries. The metal semiconductor nitride gate electrodes (40, 70) are relatively stable, can be formed relatively thinner than traditional gate electrodes (40, 70) and work functions near the middle of the band gap for the material of the substrate (12).

Abstract: A lateral power metal-oxide-semiconductor field effect transistor (MOSFET) having a gate design in which the gate structure is coupled to the gate electrode through contacts at a plurality of locations. The gate electrode is disposed over the gate structure along the length of a MOSFET finger. In one embodiment, the gate electrode is coupled to the gate structure through contacts at the ends of the MOSFET finger such that there is a contact-free portion of the gate region between the contacts.

Abstract: A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a dielectric layer (24) to provide electrical isolation. The semiconductor device (10) includes a drain extension region (101) that extend from a drain region (44) to a gate structure (20). The semiconductor device (10) also has a conductive structure (105) that is adjacent to the gate structure (20).

Abstract: There is a bi-level bit line architecture. Specifically, there is a DRAM memory cell and cell array that allows for six square feature area (6F.sup.2) cell sizes and avoids the signal to noise problems. Uniquely, the digit lines are designed to lie on top of each other like a double decker overpass road. Additionally, this design allows each digit line to be routed on both conductor layers, for equal lengths of the array, to provide balanced impedance. Now noise will appear as a common mode noise on both lines, and not as differential mode noise that would degrade the sensing operation. Furthermore, digit to digit coupling is nearly eliminated because of the twist design.

Abstract: A CMOS logic gate for a semiconductor apparatus having a buried channel NMOS transistor and a fabrication method of the same are disclosed. The CMOS logic gate according to the present invention includes a pull up unit gate-connected by an input voltage and pulling up an output voltage, a buried channel NMOS transistor connected with the pull up unit and gate-connected by a power voltage, and a surface channel NMOS transistor connected with the buried channel NMOS transistor and gate-connected by the input voltage for pulling down the output voltage for thereby enhancing a reliability of the CMOS logic gate.

Abstract: A static random access memory (SRAM) cell includes a substrate having first and second semiconductor layers, the second semiconductor layer being on the first semiconductor layer, active regions of first and second access transistors in the second semiconductor layer, gate electrodes of the first and second access transistors on the active regions, gate electrodes of first and second drive transistors in first terminals of the first and second access transistors, respectively, the gate electrodes penetrating the second semiconductor layer, first and second load resistors electrically contacting the first terminals of the first and second access transistors, respectively, and first and second bit lines electrically contacting second terminals of the first and second access transistors, respectively.

Abstract: An object of the present invention is to prevent deterioration of adhesion between a molding resin and lead frame and a light transmission characteristic due to the attachment of a translucent resin to an upper surface of the lead frame upon charging a photocoupler with the translucent resin.A concave portion is defined in an island of a lead frame to which a photosensitive semiconductor device is fixed.