Abstract: Disclosed are a semiconductor device and a method for fabricating the same which improve short channel effect and increase current driving force. The semiconductor device includes a first conductivity type semiconductor substrate, a gate electrode formed on the semiconductor substrate, a sidewall insulating film formed at both sides of the gate electrode, a second conductivity type first lightly doped impurity region and a second conductivity type second heavily doped impurity region formed in the semiconductor substrate at both sides of the gate electrode, a first conductivity type first impurity region for surrounding the second conductivity type first impurity region, and a first conductivity type second impurity region for surrounding the second conductivity type second impurity region.

Abstract: A method for forming a p-type halo implant as ROM cell isolation in a flat-cell mask ROM process is described. A P-well is formed within a semiconductor substrate and an oxide layer is formed overlying a surface of the substrate. A photomask is formed overlying the oxide layer wherein openings are left within the photomask exposing portions of the oxide layer. First, ions are implanted through the exposed portions of the oxide layer into the underlying semiconductor substrate whereby buried bit lines are formed. Thereafter, second ions are implanted through the exposed portions of the oxide layer whereby halo regions are formed encompassing the buried bit lines. The halo regions provide ROM isolation and punch-through protection for the buried bit lines. Thereafter, the photomask is removed and fabrication of flat-cell mask ROM device is completed.

Abstract: A trench-gated Schottky diode of the kind described in U.S. Pat. No. 5,365,102 is provided with an integral clamping diode which protects the gate oxide from damage from high electric fields and hot carrier generation when the device is reverse-biased. The clamping diode is arranged in parallel with the normal current path through the Schottky diode and comprises a PN junction created by a diffusion of opposite conductivity to the semiconductor material of the Schottky diode. In a preferred embodiment, the clamping diode is selected to prevent significant impact ionization near the trenched gate during either steady state- or deep depletion-induced avalanche breakdown.

Abstract: A method for fabricating a field effect transistor (FET) with a T-like gate structure includes forming a silicon nitride layer over a silicon substrate and patterning it to form an opening that exposes the substrate. A dielectric layer is formed on a lower portion of each side-wall of the opening so that the opening has a T-like free space. A doped polysilicon layer fills the T-like free space through only one deposition. After performing a planarization on the doped polysilicon layer, a titanium metal layer is formed over the substrate. A self-aligned titanium silicide is formed over the substrate other than the dielectric layer surface through a rapid thermal process (RTP). A selective etching process is performed to remove the remaining titanium metal layer. After removing the dielectric layer a RTP is performed again to reform the crystal structure of the titanium silicide layer so as to reduce its resistance. A T-like gate structure is formed.

Abstract: The present invention relates to a vertical bipolar power transistor primarily intended for radio frequency applications and to a method for manufacturing the bipolar power transistor. The power transistor comprises a substrate (13), a collector layer (15) of a first conductivity type on the substrate, a base (19) of a second conductivity type electrically connected to the collector layer, an emitter (21) of the first conductivity type electrically connected to the base, the base and the emitter each being electrically connected to a metallic interconnecting layer (31,33), the interconnecting layers (31,33) being at least in parts separated from the collector layer (15) by an insulation oxide (17). According to the invention the power transistor substantially comprises a field shield (25) electrically connected to the emitter, and located between the metallic interconnecting layer of the base and the insulation oxide.

Abstract: A semiconductor memory device, which has metal wirings on interlayer insulating films having a step on a border portion between a memory cell array region and a peripheral circuit region, and which can prevent a short-circuit between adjacent metal wirings to allow a cell area thereof to be reduced, is provided. No metal wiring is provided on a first interlayer insulating film formed on the border portion and having a large step. Connecting wirings are provided on a second interlayer insulating film formed on the border portion and having a small step to connect metal wirings of a first metal wiring layer.

Abstract: Electrically conductive lamina are attached by an electrically insulating, thermally conductive adhesive and/or solder to one or more semiconductor devices such as chips and extend beyond the periphery of the chip or chips to form heat sink fins. Electrical connections may be made between such chips through holes (e.g. by a wire or plated through hole) in the electrically conductive lamina lined with an insulating material such as the electrically insulating adhesive to provide a structurally robust assembly. Surface pads and connections may overlie patterns of insulator on the lamina. A further lamina can be wrapped around lateral sides of the assembly to provide further heat sink area and mechanical protection for other heat sink fins. A graphite/carbon fiber composite matrix material is preferred for the lamina and the coefficient of thermal expansion of such materials may be matched to that of the semiconductor material attached thereto.

Abstract: A semiconductor device that includes a recessed portion formed by isotropic-etching through an opening in an oxide layer on a surface of the semiconductor substrate, an opening formed in an oxide layer formed on the inner surface of the recessed portion by anisotropic etching, a recessed portion formed adjacent another recessed portion by isotropic etching through the opening. An overhang portion in the oxide layers at the opening is used as a mask in successive etching steps, and the isotropic and anistropic etching steps are repeated through the same mask, to eliminate errors in stacking masks and obtaining a deep notched gate structure within a short period. A cross-sectional shape of the recessed portion includes a plurality of curved recessed portions of different curvatures. A semiconductor device thus formed includes a recessed portion having a high aspect (length/width) ratio, and a depth larger than the width.

Abstract: A CMOS semiconductor device having NMOS source/drain regions formed using multiple spacers has at least one NMOS region and at least one PMOS region. A first n-type dopant is selectively implanted into an NMOS active region of the substrate adjacent a NMOS gate electrode to form a first n-doped region in the NMOS active region. A first NMOS spacer is formed on a sidewall of the NMOS gate electrode and a first PMOS spacer on a sidewall of a PMOS gate electrode. A second n-type dopant is selectively implanted into the NMOS active region using the first NMOS spacer as a mask. A p-type dopant is selectively implanted into a PMOS active region using the first PMOS spacer as a mask to form a first p-doped region in the PMOS active region. A second NMOS spacer and a second PMOS spacer are formed adjacent the first NMOS spacer and first PMOS spacer, respectively.

Abstract: Disclosed is a semiconductor device including a lateral MOS element which comprises a p-type silicon substrate; a first semiconductor layer of an n-type constituting a drift region; a second semiconductor layer of the p-type selectively provided in the first semiconductor layer, and constituting a body region, in which a channel region is partially formed; a third semiconductor layer of the n-type selectively provided in a surface of the second semiconductor layer, and constituting a source region; a fourth semiconductor layer of the n-type provided in the first semiconductor layer, and constituting a drain region; and a trench gate. The trench gate is constructed such that a trench formed in the first semiconductor layer is filled with a gate electrode with an insulating film interposed therebetween. The trench gate is formed such that at least a bottom thereof is in contact with the semiconductor substrate.

Abstract: An integrated DRAM cell comprises a DRAM capacitor and a transistor. The capacitor of the cell is formed in a first well in a dielectric layer overlying the cell transistor. The top electrode of the capacitor also serves as a barrier layer between an underlying plug in a second well in the dielectric layer. A method of forming the cell comprises the step of using a single mask for formation of the layer which acts as both the top electrode of the capacitor and the barrier layer of the second well.

Abstract: A semiconductor device including an interlayer insulation film is obtained, superior in planarization, insulation characteristics, and adhesion, suitable for microminiaturization of an element, and without inducing the problem of signal delay. In the fabrication method of this semiconductor device, an interconnection is formed on semiconductor substrate. Then, a first insulation film is formed so as to be in contact on the interconnection. Impurities are introduced into the first insulation film under a condition where the impurities arrive at least at the interconnection. As a result, the first insulation film is reduced in moisture and becomes less hygroscopic. Therefore, the insulation characteristics of the first insulation film is improved. When an SOG film superior in planarization is employed as the first insulation film, it is possible to directly form that SOG film on an underlying interconnection.

Abstract: A vertical DMOSFET includes a buried layer which is of the same conductivity type as the drain and which extends into the heavily doped substrate and approaches or extends to the surface of the epitaxial layer at a central location in the MOSFET cell that is defined by the body regions of the MOSFET. In some embodiments the upper boundary of the buried layer generally conforms to the shape of the body region, forming a dish shaped structure under the body region. A significant portion of the current flowing through the channel is drawn into the buried layer and since the buried layer represents a relatively low-resistance path, the total resistance of the MOSFET is lowered without any significant effect on the breakdown voltage. The conformal buried layer can be formed by implanting dopant into the epitaxial layer at a high energy (0.5 to 3 MeV). Before the implant, a thick oxide layer is formed in a central region of the MOSFET cell.

Abstract: An undoped GaAs layer and a GaAs active layer are formed on a GaAs semiconductor substrate in that order, and a surface of the GaAs active layer is inactivated. Thereafter, a wafer composed of the GaAs semiconductor substrate, the undoped G&As layer and the GaAs active layer is annealed at temperatures ranging from 570 to 580.degree. C. in a molecular beam epitaxy apparatus. Thereafter, the wafer is maintained at temperatures ranging from 350 to 500.degree. C., and an insulating layer made of amorphous GaAs is formed on the GaAs active layer while using tertiary-butyl-gallium-sulfide-cubane "((t-Bu)GaS).sub.4 " as a source of the insulating layer. Thereafter, the insulating layer is patterned according to a photo-lithography method to form a gate insulating layer on the GaAs active layer.

Abstract: A vacuum processing system including two or more processing units for processing wafers and a transferring unit for carrying the wafers. In this system, even when any one of the processing units becomes inoperable because of a failure, the operation of the system can be continued, and even when a processing unit in the system requires repair or maintenance at the time of the start of operation, the system can be operated using other operable processing units without subjecting the operator to danger due to improper operation. As a result, the working efficiency of the system can be increased and the safety of the operator can be secured. In this system, the cleaning of the interior of each processing unit is performed by carrying a cleaning dummy wafer into each processing unit using the transferring unit, followed by recovery of the dummy wafer after cleaning, so that processing of wafers in the processing unit can be carried out once again.

Abstract: A lateral DMOST with a drain extension 8 and a source contact entirely which overlaps the gate and thus forms a screen between the gate and the drain. The source contact 15 does not overlap the poly gate 9 but lies entirely laterally of this gate. The gate itself is provided with a low-ohmic metal contact strip 18, which results in a low gate resistance. A metal screening strip 20 is provided between this gate contact strip and the metal drain contact 16, which screening strip is connected to the source contact 15 next to the tips of the contact strip 18. Said screening strip leads to a major improvement in the power gain at high frequencies, for example in the RF range. The screening strip 20 may be realized together with the source, drain, and gate contacts in a common metal layer.

Abstract: A method for forming a semiconductor device in a semiconductor device manufacturing apparatus (20) having a sensor (30) activated extensible shuttle (28). In a fabrication environment shuttle (28) is housed within semiconductor device manufacturing apparatus (20), where an outer door (32) is closed flush with an outer wall of the apparatus (20). As a substrate carrier (38) is moved near the apparatus (20), sensor (30) activates opening of outer door (32) and extension of shuttle (28) out of the apparatus (20) into the fabrication environment. In one embodiment, shuttle (28) has a sensor which is used to determine if carrier (38) is placed on shuttle (28) within a predetermined time, allowing retraction of shuttle (28) until it is required. The present invention increases the available operative space within the fabrication environment, and provides a clean mini-environment within apparatus (20).

Abstract: Semiconductor packaged and methods for packaging semiconductor devices are provided. A method in accordance with the invention may include the steps of: attaching solder bumps on bonding pads of a wafer; cutting the wafer into individual chips, and attaching the chips to an interface board; coupling the interface board with a lead frame; and wire-bonding the bump pads of the interface board and the inner leads of the lead frame, and carrying out a molding process.

Abstract: A ferroelectric memory cell for storing information. The information is stored in the remnant polarization of a ferroelectric dielectric layer by setting the direction of the remnant polarization. The ferroelectric memory cell is designed to store the information at a temperature less than a first temperature. The memory cell includes top and bottom contacts that sandwich the dielectric layer which includes a ferroelectric material having a Curie point greater than the first temperature and less than 400.degree. C. The dielectric layer is encapsulated in an oxygen impermeable material such that the encapsulating layer prevents oxygen from entering or leaving the dielectric layer. The memory also includes a hydrogen barrier layer that inhibits the flow of oxygen to the top and bottom electrodes when the memory cell is placed in a gaseous environment containing hydrogen. In one embodiment of the invention, a hydrogen absorbing layer is included.

Abstract: In a functional device having a substrate, source and drain regions are formed on the substrate. Each of them includes first electric charge carriers. Each of the first electric charge carriers has the substantially same first spin direction which is fixed to a predetermined direction. An intermediate region is formed between the source and drain regions and includes second electric charge carriers. Each of the second electric charge carries has a second spin direction which is variable. A current line is formed over the intermediate region and applies an external magnetic field to the intermediate region. The second direction is determined in dependency upon the application of the external magnetic filed.