Patents Examined by Donghai D. Nguyen
  • Patent number: 11710585
    Abstract: A method of removing a foil shield from a cable includes positioning the cable proximate a heating source, monitoring a characteristic of the cable or the heating source with at least one sensor, heating the foil shield in a designated area to weaken the foil shield, and removing an outer insulation of the cable and the foil shield.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: July 25, 2023
    Assignee: TE Connectivity Solutions GmbH
    Inventors: Matthew Steven Houser, Joseph Stachura, Mark Andrew Ondo, Matthew Orlowski, Amgad Ghaly, Alexandra Spitler
  • Patent number: 11706873
    Abstract: A method for manufacturing a multilayer wiring substrate includes forming a resist layer having mask pattern, forming a conductor layer having conductor pattern using the resist layer, removing the resist layer, forming an insulating layer on the conductor layer such that the insulating layer is laminated on the conductor layer, forming a subsequent resist layer having mask pattern such that the subsequent resist layer is formed on the insulating layer, and forming a subsequent conductor layer having conductor pattern using the subsequent resist layer. The forming of the resist layer includes conducting first correction in which formation position of entire mask pattern of the resist layer is corrected with respect to reference position, and conducting second correction in which shape of the mask pattern of the resist layer is corrected with respect to reference shape, and the forming of the subsequent resist layer does not include conducting the second correction.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: July 18, 2023
    Assignee: IBIDEN CO., LTD.
    Inventor: Shigeto Iyoda
  • Patent number: 11695245
    Abstract: A crimping die including a first die piece having a recess portion and a second die piece having a protrusion portion is provided. An inner wall surface of the recess portion has a bottom wall surface and recess-side lateral end surfaces. An outer surface of the protrusion portion has a top end surface and protrusion-side lateral end surfaces. The bottom wall surface has a recess-side projection portion, a recess-side concave portion, and a recess-side curvature changing portion. The top end surface has a protrusion-side projection portion, a protrusion-side concave portion, and a protrusion-side curvature changing portion. A sign of curvature of the bottom wall surface changes at a boundary portion in the recess-side curvature changing portion with respect to the recess-side concave portion. A sign of curvature of the top end surface changes at a boundary portion in the protrusion-side curvature changing portion with respect to the protrusion-side concave portion.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: July 4, 2023
    Assignee: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
    Inventor: Kiyohito Koide
  • Patent number: 11690177
    Abstract: Methods and systems for making a multi-layer circuit board are disclosed, including electrically connecting a boring device with a plated multi-layered circuit board; cutting a first bore having a first diameter through a first layer of the plated multi-layered circuit board; reciprocally extending a second cutting device a first predetermined distance into a barrel plated multi-layered circuit board and retracting the cutting device a second predetermined distance that is less than the first predetermined distance to form a second bore; after each retraction, sensing for electrical contact indicating a closed circuit between the cutting device and the plated multi-layered circuit board; if a closed circuit is sensed, determining if the second bore has reached an expected depth of a contact layer; and if the expected depth of the contact layer has not been reached, determining that a sliver has been formed in the barrel.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: June 27, 2023
    Assignee: NextGin Technology BV
    Inventor: J.A.A.M. Tourne
  • Patent number: 11690180
    Abstract: A manufacturing method of a carrier structure includes: A build-up circuit layer is formed on a carrier. The build-up circuit layer includes at least one first circuit layer, at least one first dielectric layer, a second circuit layer, a second dielectric layer, and a plurality of conductive vias. The first circuit layer is located on the carrier and includes at least one first pad, which is disposed relative to at least one through hole of the carrier. The first dielectric layer is located on the first circuit layer. The second circuit layer is located on the first dielectric layer and includes at least one second pad. The second dielectric layer is located on the second circuit layer and includes at least one opening exposing the second pad. The conductive via penetrates the first dielectric layer and is electrically connected to the first circuit layer and the second circuit layer.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: June 27, 2023
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Cheng-Ta Ko, Pu-Ju Lin, Tse-Wei Wang
  • Patent number: 11683888
    Abstract: A package circuit structure includes a multilayer circuit board, an electronic component, and an insulating layer. The multilayer circuit board includes a metal portion and an opening. The opening is extending from a first side of the multilayer circuit board toward the second side of the multilayer circuit board facing the first side. A bottom of the opening is sealed by the metal portion. The electronic component is received in the opening and adhered to the metal portion. The electronic component is electrically connected to the multilayer circuit board and encapsulated in the opening by the insulating layer. A method for manufacturing the package circuit structure is also provided.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: June 20, 2023
    Assignees: Leading Interconnect Semiconductor Technology Qinhuangdao Co, Ltd., Qi Ding Technology Qinhuangdao Co, Ltd., Leading Interconnect Semiconductor Technology (ShenZhen) Co, Ltd.
    Inventors: Chun-Chieh Huang, Chin-Ming Liu
  • Patent number: 11683922
    Abstract: A component mounting system includes multiple component mounting lines where multiple component mounters and a feeder storage are aligned along a board conveyance direction, a feeder exchange device configured to move along the board conveyance direction to exchange the feeder between the component mounter and the feeder storage of the component mounting line in charge, and a memory device. The feeder exchange device is configured to store an in-process feeder in the feeder storage of the component mounting line in charge, when it is determined, based on production information and feeder information, that there is the in-process feeder that was used in the component mounting line in charge and is scheduled to be used in another component mounting line.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 20, 2023
    Assignee: FUJI CORPORATION
    Inventor: Hidetoshi Kawai
  • Patent number: 11683891
    Abstract: A method of inspecting a printed wiring board includes preparing a printed wiring board having product and inspection regions such that the board has inner-layer lands in the regions, forming vias on the inner-layer lands in the regions, forming outer peripheral part(s) in the wiring board such that the outer peripheral part(s) expose outer peripheral portion(s) of the inner-layer land in the inspection region, determining a center coordinate of the inner-layer land in the inspection region based on a position of the outer peripheral part(s), determining a center coordinate of the via(s) in the inspection region based on a shape of the via(s) in the inspection region, determining a misalignment amount based on a distance between the center coordinate of the inner-layer land and the center coordinate of the via(s) in the inspection region, and determining alignment accuracy between the via and the inner-layer land based on the misalignment amount.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: June 20, 2023
    Assignee: IBIDEN CO., LTD.
    Inventor: Yasuhiro Kawai
  • Patent number: 11678441
    Abstract: A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: June 13, 2023
    Assignee: Unimicron Technology Corp.
    Inventors: Wei-Ti Lin, Chun-Hsien Chien, Chien-Chou Chen, Fu-Yang Chen, Ra-Min Tain
  • Patent number: 11677205
    Abstract: An inter-device cabling movement system includes a base and a plurality of cable attachment devices that extend from the base in a port identification sequence. Each of the plurality of cable attachment devices includes a cable engagement element that is configured to engage a respective cable, and a cable securing element that is configured to secure the cable engagement element to the respective cable. The cable engagement elements and cable securing elements may be utilized to secure each cable attachment device to respective cables connected to first ports on a first device so that those respective cables may be disconnected from the first pots on the first device and reconnected to second ports on a second device based on the port identification sequence.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: June 13, 2023
    Assignee: Dell Products L.P.
    Inventors: Shree Rathinasamy, Kannan Karuppiah, Neal Beard
  • Patent number: 11665831
    Abstract: A method for manufacturing a circuit board with nickel resistor embedded therein provides a copper substrate, the copper substrate includes a copper foil. A nickel resistance layer is formed on the copper foil. A first dielectric layer and a first copper layer are formed on the nickel resistance layer. The copper foil and the first copper layer are etched to form a first conductive wiring layer and a second conductive wiring layer respectively, the nickel layer not being subjected to an etching process, to obtain the finished circuit board.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: May 30, 2023
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventors: Jian Wang, Mei Yang
  • Patent number: 11647593
    Abstract: A printed circuit board has an in-pad via. In a first step, a component is mounted on a first surface of a printed circuit board. A screen to be used in a second step has openings at positions corresponding to those of a plurality of pads on a second surface and has a recess positioned to overlap an in-pad via. Solder cream is applied from above the screen, and the screen is removed. Then, a component is mounted on the second surface.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: May 9, 2023
    Assignee: Sony Interactive Entertainment Inc.
    Inventors: Kazuki Sasao, Katsushi Wada
  • Patent number: 11638372
    Abstract: Techniques described herein relate to integrating an electronic component into a ceiling mount in a ceiling tile system so as to maintain the aesthetic integrity of the ceiling while providing a suitable structural system to secure the equipment into the ceiling.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: April 25, 2023
    Assignee: AmpThink, LLC
    Inventor: William C. Anderson, III
  • Patent number: 11627668
    Abstract: A circuit board includes a circuit substrate, a solder, and a surrounding portion. The circuit substrate includes a connecting pad. The solder is formed on a surface of the connecting pad. The surrounding portion is formed on the surface of the connecting pad and cooperates with the connecting pad to form a groove receiving the solder. The surrounding portion surrounds the solder and is spaced from the solder. A method for manufacturing a circuit board is also provided.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: April 11, 2023
    Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., GARUDA TECHNOLOGY CO., LTD.
    Inventors: Yong-Chao Wei, Po-Yuan Chen
  • Patent number: 11618103
    Abstract: A method and fixture for welding a battery foil-tab assembly is disclosed. The fixture includes a first clamp member having a first clamping surface defining an opening extending into the first clamp member and a second clamp member having a protrusion surrounding a weld slot. The opening of the first clamp member is configured to receive a portion of the protrusion with the battery foil-tab assembly disposed therebetween. The second clamp member is moveable toward the first clamp member to align the weld slot of the second clamp member with the opening of the first clamp member, thereby causing the protrusion to cooperate with the opening of the first clamp to deflect a portion of the battery foil-tab assembly out of a plane parallel with the battery foil-tab assembly. A laser beam is directed at the out of plane portion to laser weld the battery foil-tab assembly.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 4, 2023
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Teresa J. Rinker, Hongliang Wang, Chih-Chang Chen, Erik B. Golm
  • Patent number: 11607759
    Abstract: The present disclosure relates to systems, apparatuses, and methods for assembling cartridges for aerosol delivery devices. The cartridges may be assembled by coupling a base of the cartridge to a carriage that is transported via a track. The track transports the carriages between various substations at which one or more parts are added to the base. The carriage may be lifted from the track by a lifter mechanism at each substation in order to perform assembly operations on the base. An inspection system may inspect the cartridges at various stages of completion at or between the various substations.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: March 21, 2023
    Assignee: RAI Strategic Holdings, Inc.
    Inventors: Quentin Paul Guenther, Jr., Johnny Keith Cagigas, William Robert Collett, Lawrence P. Balash, Scott Lee Brady, Ronnie Dean Dover, John Scott Gerow, Don Edward Green, John Matthew Odel, Christopher M. Spencer, Vernon L. Steiner, David James Thierauf, Louis Wade Wacker, Byron Joseph Williams
  • Patent number: 11611193
    Abstract: A surface mountable laser driver circuit package is configured to mount on a host printed circuit board (PCB). A surface mount circuit package includes a lead-frame. A plurality of laser driver circuit components is mounted on and in electrical communication with the lead-frame of the surface mount circuit package. A dielectric layer is located between the lead-frame and the host PCB and includes portals through the dielectric layer each arranged to accommodate an electrical connection between the lead-frame and the host PCB. The lead-frame and the dielectric layer are arranged such that a first lead-frame portion and a first dielectric layer portal align with a first end of a host PCB trace configured to provide a current return path for the surface mount laser driver, and a second lead-frame portion and a second dielectric layer portal align with a second end of the host PCB trace.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: March 21, 2023
    Assignee: Excelitas Canada, Inc.
    Inventors: Gabriel Charlebois, JinHan Ju, Lawrence Godfrey
  • Patent number: 11611187
    Abstract: An electrical connector assembling machine includes a connector strip feed unit including a connector strip feeding device configured to index a connector strip through a feed track in successive feed strokes and a contact loading assembly to load contacts in the connector strip. The electrical connector assembling machine includes a contact bending assembly positioned downstream of the contact loading assembly. The contact bending assembly includes a roller and a bending actuator holding the roller. The bending actuator moves the roller in an actuation direction to engage and bend ends of the contacts. The roller rolling along the contacts to bend the ends of the contacts.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: March 21, 2023
    Inventors: David Wiltraut, Scott Thomas Schlegel
  • Patent number: 11606864
    Abstract: Systems and methods for improved interconnections for electronic components using ACAs are provided. The methods involve using magnets specific for each component to be connected and optimized in terms of size and strength and position relative to the substrate and component. Also provided are ovens adapted for use with the methods and systems and kits providing the parts of the system for use with existing ovens.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: March 14, 2023
    Assignee: SunRay Scientific, Inc.
    Inventor: Andrew Stemmermann
  • Patent number: 11602056
    Abstract: Circuit board includes conductive plate, core dielectric layer, metallization layer, first build-up stack, second build-up stack. Conductive plate has channels extending from top surface to bottom surface. Core dielectric layer extends on covering top surface and side surfaces of conductive plate. Metallization layer extends on core dielectric layer and within channels of conductive plate. Core dielectric layer insulates metallization layer from conductive plate. First build-up stack is disposed on top surface of conductive plate and includes conductive layers alternately stacked with dielectric layers. Conductive layers electrically connect to metallization layer. Second build-up stack is disposed on bottom surface of conductive plate. Second build-up stack includes bottommost dielectric layer and bottommost conductive layer. Bottommost dielectric layer covers bottom surface of conductive plate.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chen-Hua Yu, Chung-Shi Liu