Abstract: A package-board co-design methodology preserves the signal integrity of high-speed signals passing from semiconductor packages to application PCBs. An optimal architecture of interconnects between package and PCB enhances the signal propagation, minimizes parasitic levels, and decreases electromagnetic interference from adjacent high frequency signals. The invention results in devices with superior signal quality and EMI shielding properties with enhanced capability for carrying data stream at multiple-gigabit per second bit-rates.

Abstract: A display device is provided in which contact holes, each having a sidewall with an ideal tapered shape, are formed in a structure in which a silicon oxide film, a silicon nitride film and a silicon oxide film are stacked in the named order. The display device includes a first silicon oxide film, a silicon nitride film stacked on the first silicon oxide film, a second silicon oxide film stacked on the silicon nitride film, and a contact hole which extends through at least these three layers. In the display device, letting d2 and d3 denote, respectively, a film thickness of the silicon nitride film and a film thickness of the second silicon oxide film, these films are stacked to satisfy the relationship d2<d3, and the contact hole is formed to have a tapered shape free of constrictions.

Abstract: The memory cell matrix encompasses (a) a plurality device isolation films running along column direction, (b) first conductive layers arranged along row and column-directions, adjacent groups of the first conductive layers are isolated from each other by the device isolation film disposed between the adjacent groups, (c) lower inter-electrode dielectrics arranged respectively on crests of the corresponding first conductive layers, (d) an upper inter-electrode dielectric arranged on the lower inter-electrode dielectric made of insulating material different from the lower inter-electrode dielectrics, and (e) second conductive layers running along the row-direction, arranged on the upper inter-electrode dielectric.

Abstract: A borderless contact structure and method of fabricating the structure, the method including: (a) providing a substrate; (b) forming a polysilicon line on the substrate, the polysilicon line having sidewalls; (c) forming an insulating sidewall layer on the sidewalls of the polysilicon line; (d) removing a portion of the polysilicon line and a corresponding portion of the insulating sidewall layer in a contact region of the polysilicon line; and (e) forming a silicide layer on the sidewall of the polysilicon line in the contact region. Also an SRAM cell using the borderless contact structure and a method of fabricating the SRAM cell.

Abstract: A method and system for providing a magnetic element is disclosed. The method and system include providing a free layer, a spacer layer, and a pinned layer. The free layer is ferromagnetic and has a free layer magnetization. The spacer layer is nonmagnetic and resides between the pinned and free layers. The pinned layer includes first and second ferromagnetic layers having first and second magnetizations, a nonmagnetic spacer layer, and a spin depolarization layer. Residing between the first and second ferromagnetic layers, the nonmagnetic spacer layer is conductive and promotes antiparallel orientations between the first and second magnetizations. The spin depolarization layer is configured to depolarize at least a portion of a plurality of electrons passing through it. The magnetic element is also configured to allow the free layer magnetization to change direction due to spin transfer when a write current is passed through the magnetic element.

Abstract: A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region therebetween. A gate opposes the floating body region and is separated therefrom by a gate oxide on a first side of the vertical transistor. A floating body back gate opposes the floating body region on a second side of the vertical transistor and is separated therefrom by a dielectric to form a body capacitor.

Abstract: A cell transistor includes source/drain regions formed at a lower level than part of its channel region. A select transistor has a channel region and source/drain regions formed at substantially the same level as the source/drain regions of the cell transistor. One of the source/drain regions of the cell transistor and one of the source/drain regions of the select transistor are electrically interconnected to each other in substantially the same plane.

Abstract: A method for fabricating an in-plane switching LCD device includes forming a data line and a light-shielding layer on a substrate, forming a pixel electrode line and an active region with a polycrystalline silicon thin film, forming a first insulating layer on the substrate, forming a gate electrode and a common electrode line on the first insulating layer, forming a second insulating layer on the substrate, forming a first contact hole that exposes at least portions of the data line and the active region, and forming a connection electrode that connects at least portions of the exposed data line and the active region.

Abstract: The present invention provides an electronic device comprising a base substrate to be surface-mounted on a circuit board, one or more electronic component elements mounted on a surface of the base substrate and/or therein, an external electrode provided on an end portion of the base substrate and in the form of a post perpendicular to a rear surface of the base substrate for connecting the one or more electronic component elements to the circuit board. Furthermore, the base substrate is provided on its end portion with a slope crossing a side surface and a rear surface of the base substrate. A surface of the external electrode is exposed on the slope.

Abstract: Provided is an electroluminescent display device having a negligibly small voltage drop of a cathode, no external light reflection, and high contrast and luminance. The electroluminescent display device includes a rear substrate, a first electrode layer formed above the rear substrate, a second electrode layer formed above the first electrode layer, the second electrode layer facing the first electrode layer, a light-emitting layer interposed between the first electrode layer and the second electrode layer, the light-emitting layer having at least an emission layer, a front substrate facing the rear substrate and contacting an upper surface of the second electrode layer, and a functional thin film formed between the second electrode layer and the front substrate, the functional thin film having a conductive material at least in a portion thereof contacting the second electrode layer.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) device is provided that includes a localized strained device channel and adjoining source/drain junctions that are unstrained. The MOSFET device has a very high channel carrier mobility, while maintaining a very low leakage junction.

Abstract: Provided is an electroluminescent display device having a negligibly small voltage drop of a cathode, no external light reflection, and high contrast and luminance. The electroluminescent display device includes a rear substrate, a first electrode layer formed above the rear substrate, a second electrode layer formed above the first electrode layer, the second electrode layer facing the first electrode layer, a light-emitting layer interposed between the first electrode layer and the second electrode layer, the light-emitting layer having at least an emission layer, a front substrate facing the rear substrate and contacting an upper surface of the second electrode layer, and a functional thin film formed between the second electrode layer and the front substrate, the functional thin film having a conductive material at least in a portion thereof contacting the second electrode layer.

Abstract: An MTJ MRAM cell element, whose free layer has a shape induced magnetic anisotropy, is formed between orthogonal word and bit lines. The bit line is a composite line which includes a high conductivity current carrying layer and a soft adjacent magnetic layer (SAL). During operation, the soft magnetic layer concentrates the magnetic field of the current and, due to its proximity to the free layer, it magnetically couples with the free layer to produce two magnetization states of greater and lesser stability. During switching, the layer is first placed in the less stable state by a word line current, so that a small bit line current can switch its magnetization direction. After switching, the state reverts to its more stable form as a result of magnetostatic interaction with the SAL, which prevents it from being accidentally rewritten when it is not actually selected and also provides stability against thermal agitation.

Abstract: Transistors and methods of fabricating transistors are disclosed. A disclosed method comprises forming an inversion epitaxial layer on a silicon substrate; forming a hard mask on the inversion epitaxial layer; depositing a silicon epitaxial layer over the inversion epitaxial layer; forming a trench through the silicon epitaxial layer by removing the hard mask; forming reverse spacers on the sidewalls of the trench by filling the trench with an insulating layer and etching the insulating layer; forming a gate electrode over the reverse spacers; forming pocket-well regions and LDD regions in the silicon substrate by performing ion implantations; forming spacers on the sidewalls of the gate electrode; forming source and drain regions in the silicon substrate by performing an ion implantation; and forming a silicide layer on the gate electrode and the source and drain regions.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: A memory cell structure and control of the memory operation are simplified, and the cost of production is decreased, by way of a semiconductor nonvolatile memory having a transistor including a gate electrode provided on a p-type semiconductor substrate via a gate insulating film, and a source region and a drain region, which are a pair of n-type impurity diffusion regions in the surface layer region of the semiconductor substrate at positions sandwiching the gate electrodes therebetween. A first resistance-varying portion and a second resistance-varying portion are sandwiched by the source region, drain region and channel-forming region. The n-type impurity concentration in the resistance-varying portions is lower than in the source and drain regions.

Abstract: The disclosed embodiments relate to a plurality of capacitive memory elements disposed on a substrate. The substrate may comprise a processor, a memory device or other integrated circuit device. The capacitive memory elements may have a generally oblong shape and may be capacitive elements. The capacitive memory elements may be disposed in a slanted orientation. The capacitive memory elements may be disposed in a non-orthogonal orientation. The capacitive memory elements may be disposed so that an axis through one of the plurality of capacitive memory elements is not generally parallel with an edge of the substrate. The axis may not be generally perpendicular with an orthogonal edge of the substrate. The plurality of capacitive memory elements may be arranged in a first row and a second row so that an axis through one of the plurality of capacitive memory elements located in the first row does not form an axis of any capacitive memory element in the second row.

Abstract: A semiconductor storage device includes a semiconductor substrate; an sulating layer formed on the semiconductor substrate; a first semiconductor layer formed on the insulating layer and insulated from the semiconductor substrate; memory cells each having a source region of a first conduction type and a drain region of the first conduction type both formed in the first semiconductor layer, and having a body of a second conduction type formed in the first semiconductor layer between the source region and the drain region, the memory cells being capable of storing data by accumulating or releasing electric charge in or from their respective body regions; memory cell lines each including a plurality of the memory cells aligned in the channel lengthwise direction; and a memory cell array including a plurality of the memory cell lines aligned in a channel widthwise direction of the memory cells.

Abstract: An EEPROM device manufacturing method is disclosed. The method includes the steps of oxidation, polysilicon deposition, and etching to form first polysilicon layers of a select transistor and a floating gate electrode. The method also includes a second polysilicon deposition step followed by an etching step to form a logic gate electrode and a control gate electrode at the same time. This method prevents damage to the silicon substrate and reduces the number of process steps compared to conventional manufacturing methods.

Abstract: The disclosed embodiments relate to a plurality of capacitive memory elements disposed on a substrate. The substrate may comprise a processor, a memory device or other integrated circuit device. The capacitive memory elements may have a generally oblong shape and may be capacitive elements. The capacitive memory elements may be disposed in a slanted orientation. The capacitive memory elements may be disposed in a non-orthogonal orientation. The capacitive memory elements may be disposed so that an axis through one of the plurality of capacitive memory elements is not generally parallel with an edge of the substrate. The axis may not be generally perpendicular with an orthogonal edge of the substrate. The plurality of capacitive memory elements may be arranged in a first row and a second row so that an axis through one of the plurality of capacitive memory elements located in the first row does not form an axis of any capacitive memory element in the second row.