Abstract: A semiconductor multi-package module having a second package stacked over a lower ball grid array first package, each package including a die attached to a substrate, in which the first and second package substrates are interconnected by wire bonding. Also, a method for making a semiconductor multi-package module, by providing a ball grid array first package including a substrate and a die, affixing a second package including a substrate and a die onto an upper surface of the lower package, and forming z-interconnects between the first and lower substrates.

Abstract: A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.

Abstract: A semiconductor memory device includes a first wiring layer, a second wiring layer, a memory cell, and a contact plug. The first wiring layer is formed in an interlayer insulating film. The second wiring layer is formed on the interlayer insulating film. The memory cell includes a first ferromagnetic film formed on the second wiring layer, a tunnel barrier film formed on the first ferromagnetic film, and a second ferromagnetic film formed on the tunnel barrier film. The contact plug is formed on the first wiring layer and connects the first wiring to the second wiring layer, and the upper surface of the contact plug is in a position higher than that of the second wiring layer.

Abstract: The disclosed embodiments relate to a plurality of capacitive memory elements disposed on a substrate. The substrate may comprise a processor, a memory device or other integrated circuit device. The capacitive memory elements may have a generally oblong shape and may be capacitive elements. The capacitive memory elements may be disposed in a slanted orientation. The capacitive memory elements may be disposed in a non-orthogonal orientation. The capacitive memory elements may be disposed so that an axis through one of the plurality of capacitive memory elements is not generally parallel with an edge of the substrate. The axis may not be generally perpendicular with an orthogonal edge of the substrate. The plurality of capacitive memory elements may be arranged in a first row and a second row so that an axis through one of the plurality of capacitive memory elements located in the first row does not form an axis of any capacitive memory element in the second row.

Abstract: The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (GexSe1-x) to be doped with a metal such as silver, copper, or zinc without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with the metal. The chalcogenide glass doped with the metal can be used to store data in a memory device. Advantageously, the systems and methods co-sputter the metal and the chalcogenide glass and allow for relatively precise and efficient control of a constituent ratio between the doping metal and the chalcogenide glass. Further advantageously, the systems and methods enable the doping of the chalcogenide glass with a relatively high degree of uniformity over the depth of the formed layer of chalcogenide glass and the metal. Also, the systems and methods allow a metal concentration to be varied in a controlled manner along the thin film depth.

Abstract: A copackaged electronic device comprises a diode device having an anode coupled to a drain electrode of a switching device and a cathode capable of being coupled to an external circuit. The switching device may be controlled by an integrated circuit mounted on a source electrode of the switching device and electrically connected such that the integrated circuit is capable of controlling switching of the switching device. For example, the device is used in a power factor correction circuit. The diode device comprises at least one inverted diode having a solderable anode and a wire-bondable cathode.

Abstract: A liquid crystal device is provided that comprises a plurality of R colored layers, a plurality of G colored layers, and a plurality of B colored layers that are formed on either one of a pair of substrates and are aligned in a predetermined arrangement in plan view, a light-shielding layer formed between the colored layers, and a plurality of spacers formed on either one of the pair of substrates and protruding toward the other substrate. The plurality of spacers is formed around the B colored layers and/or the R colored layers, but is not formed around the G colored layers. Thus, even if a positional deviation occurs between the substrates, the spacers do not get into the G colored layers.

Abstract: In a process for fabricating a ferrocapacitor comprising providing ferroelectric PZT elements over an Al2O3 layer, the Al2O3 layer is covered with a seed layer comprising layers of PZT and TiO2. Then a thicker layer of PZT is formed over the seed layer and crystallized. By this process, the crystallinity of the thick PZT layer is much improved, and its orientation is improved to be in the (111) direction. Furthermore, the seed layer reduces downward diffraction of Pb from the thick PZT layer, such as through the Al2O3 into a TEOS structure beneath.

Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells for memory devices and electronic systems. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb.

Abstract: This invention relates to a semiconductor structure for dual damascene processing and includes upper and lower low k dielectric layers formed in a stack when the upper surface of the lower layer has an integral etch stop layer formed by exposing the upper surfaces of the layer H2 plasma without any prior anneal prior to the deposition of the upper layer.

Abstract: An improved semiconductor device is disclosed with a NMOS transistor formed on a P-Well in a deep N-well, a PMOS transistor formed on a N-Well in the deep N-well, a first voltage coupled to a source node of the PMOS, and a second voltage higher than the first voltage coupled to the N-well, wherein the second voltage expands a depletion region associated with the PMOS and NMOS transistor for absorbing electrons and holes caused by alien particles.

Abstract: A mold is filled with unsintered SiC particles and a melt of Al or of an Al alloy containing Si is poured into the mold for high pressure casting. Owing to the SiC particles and Si precipitated upon casting, a low expansion material having a low thermal expansion coefficient is produced. A heat transmission path is formed by Al infiltrating spaces between the SiC particles and therefore high heat conductivity is obtained.

Abstract: A low resistance copper damascene interconnect structure is formed by providing a thin dielectric film such as SiC or SiOC formed on the sidewalls of the via and trench structures to function as a copper diffusion barrier layer. The dielectric copper diffusion barrier formed on the bottom of the trench structure is removed by anisotropic etching to expose patterned metal areas. The residual dielectric thus forms a dielectric diffusion barrier film on the sidewalls of the structure, and coupled with the metal diffusion barrier subsequently formed in the trench, creates a copper diffusion barrier to protect the bulk dielectric from copper leakage.

Abstract: A method of forming a SiCOH etch stop layer in a copper damascene process is described. A substrate with an exposed metal layer is treated with H2 or NH3 plasma to remove metal oxides. Trimethylsilane is flowed into a chamber with no RF power at about 350° C. to form at least a monolayer on the exposed metal layer. The SiCOH layer is formed by a PECVD process including trimethylsilane and CO2 source gases. Optionally, a composite SiCOH layer comprised of a low compressive stress layer on a high compressive stress layer is formed on the substrate. A conventional damascene sequence is then used to form a second metal layer on the exposed metal layer. Via Rc stability is improved and a lower leakage current is achieved with the trimethylsilane passivation layer. A composite SiCOH etch stop layer provides improved stress migration resistance compared to a single low stress SiCOH layer.

Abstract: This invention proposes a stable magnetic memory device that is equipped with a storage cell having a MTJ, wherein variation in the coercive force (Hc) of a ferromagnetic free layer is suppressed, and a switching characteristic of a bit of a MRAM is improved, and there is no write error. Namely in a magnetic memory device equipped with a first wiring, a second wiring (bit line) intersecting with the first wiring, and a storage cell for writing/reading information of a magnetic spin at an intersecting area of the first wiring and the second wiring, a partial sidewall portion electrically connecting to the storage cell of the second wiring (bit line) has a forward tapered form having a contact angle relative to a top surface of the storage cell being 45 degrees or more.

Abstract: MRAMs are provided with cells offering low current leakage for partially selected cells. MRAM cells are made with magnetic tunnel junctions having barriers that meet predetermined low barrier heights and predetermined thicknesses. The barrier heights are preferably about 1.5 eV or less. The predetermined thicknesses are calculated to meet power and speed requirements. The predetermined low barrier heights and predetermined thicknesses modify a nonlinear term relating current through to voltage across the magnetic tunnel junction. The modification of the nonlinear term also modifies the amount of current that flows through a magnetic tunnel junction at various voltages. At low voltages, current through the magnetic tunnel junction will be disproportionately lower than current through a conventional magnetic tunnel junction. This decreases leakage current through partially selected MRAM cells and power.

Abstract: Embodiments of a transition metal alloy having an n-type or p-type work function that does not significantly shift at elevated temperature. The disclosed transition metal alloys may be used as, or form a part of, the gate electrode in a transistor. Methods of forming a gate electrode using these transition metal alloys are also disclosed.

Abstract: The present invention relates to a semiconductor device with an improved contact margin between an interconnection line and a bit line and a method for fabricating the same. The semiconductor device includes: a bit line structure formed on a substrate and having a number of bit lines and a pad; a first inter-layer insulation layer formed on the bit line structure and the substrate and having a first opening exposing the pad; a conductive layer formed on the first inter-layer insulation layer and patterned to be a middle pad filled into the first opening and a plate electrode of a capacitor; a second inter-layer insulation layer formed on the first inter-layer insulation layer and the patterned conductive layer and having a second opening exposing the middle pad; and a metal layer filled into the second opening to form an interconnection line contacted to the pad.

Abstract: A method of manufacturing an electro-optical device, the electro-optical device having an electro-optical element formed by laminating a first electrode, an electro-optical layer, and a second electrode in sequence on a base body, the method of manufacturing the electro-optical device, including the steps of: forming an ultraviolet absorbing layer on the substrate by a vapor deposition method so as to cover the electro-optical element; and forming a gas barrier layer by a vapor deposition method using plasma so as to cover the ultraviolet absorbing layer.

Abstract: A silicon-on-insulator (SOI) memory device (such as an SRAM) using negative differential resistance (NDR) elements is disclosed. Body effect performances for NDR FETs (and other FETs) that may be used in such device are enhanced by floating a body of some/all the NDR FETs.