Abstract: The invention relates to a nonvolatile NOR two-transistor semiconductor memory cell, an associated semiconductor memory device and a method for the fabrication thereof, in which one-transistor memory cells are located in an active region formed in annular fashion and are driven via associated word lines. In this case, the source regions of the one-transistor memory cells are connected via a source line, while the drain regions are connected via corresponding drain lines. A reduced space requirement for the two-transistor semiconductor memory cell is obtained in particular on account of the annular structure of the active regions.

Abstract: A method and system for providing a magnetic element capable of being written using spin-transfer effect while being thermally stable and a magnetic memory using the magnetic element are disclosed. The magnetic element includes a first, second and third pinned layers, first and second nonmagnetic layers, a free layer and a nonmagnetic spacer layers. The first, second and third pinned layers are ferromagnetic and have first, second and third magnetizations pinned in first, second and third directions. The first and second nonmagnetic layers include first and second diffusion barriers, respectively. The first and second nonmagnetic layers are between the first and second pinned layers and the second and third pinned layers, respectively. The first and second pinned layers and the second and third pinned layers are antiferromagnetically coupled. The nonmagnetic spacer layer is conductive and resides between the free layer and the third pinned layer.

Abstract: A SOI MOSFET 10 may be formed from silicon single crystal as a substrate body that is formed on an embedded oxide film 11. For example, a P-type body 12, a channel section 13, and N-type source region 14 and drain region 15 are formed therein. Low concentration N-type extension regions 18, a gate electrode 17 provided through a gate dielectric layer 16 and sidewalls 19 are formed therein. A body terminal 101 in which a resistance (body resistance) Rb between itself and a body is positively increased is provided, and the body terminal 101 is connected to a source region 14. This structure realizes a SOI MOSFET with a BTS (Body-Tied-to-Source) operation accompanied by a transient capacitive coupling of a body during a circuit operation.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: A method for fabricating an MIM capacitor on a substrate. A region of the substrate is dedicated for use as an electrode area of the MIM capacitor. The electrode area of the MIM capacitor may be increased by utilizing at least one spacer formed on an associated planar metal surface, wherein the planar metal surface is formed upon the substrate. An increase in a gain factor of the electrode area is thus dependent upon an associated spacer height and particular number of islands or vias. A roughened surface is thus created for use as a roughened electrode for subsequent capacitor processes. Fabricating spacers made of conducting or non-conducting materials on the associated planar metal surface can create such an electrode. The MIM capacitor formed thereof can be utilized in mixed-signal and RF applications and is fully compatible with COMS logic fabrication processes.

Abstract: The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thus incorporated into the tunnel dielectric, along with nitrogen. The gate stack is etched and completed, including protective sidewall spacers and dielectric cap, and the stack lined with a barrier to hydroxyl and hydrogen species. Though the liner advantageously reduces impurity diffusion through to the tunnel dielectric and substrate interface, it also reduces hydrogen diffusion in any subsequent hydrogen anneal. Hydrogen is provided to the tunnel dielectric, however, in the prior exposure to ammonia.

Abstract: A semiconductor device has an alternating conductivity type layer that improves the tradeoff relation between the ON-resistance and the breakdown voltage and a method of manufacturing such a semiconductor device. The alternating conductivity type layer is formed of n-type drift regions and p-type partition regions alternately arranged with each other. At least the n-type drift regions or p-type partition regions are formed by ion implantation under an acceleration voltage changed continuously. The p-type partition regions or n-type drift regions are formed by epitaxial growth or by diffusing impurities from the surface of a substrate or a layer for the layer.

Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.

Abstract: In a polycrystalline silicon thin film transistor, a semiconductor device having a high field effect mobility is achieved by increasing a grain size of a silicon thin film. First, an insulation layer having a two-layer structure is formed on a transparent insulated substrate 201. In the insulation layer, a lower insulation layer 202, which is in contact with the transparent insulating substrate 201, is made to have a higher thermal conductivity than an upper insulation layer 203. Thereafter, the upper insulation layer 203is patterned so that a plurality of stripes are formed thereon. Subsequently, an amorphous silicon thin film 204 is formed on the patterned insulation layer, and the insulation layer is irradiated with a laser light scanning in a direction parallel to the stripe pattern on the upper insulation layer 203. Thus, the amorphous silicon thin film 203 is formed into a polycrystalline silicon thin film 210.

Abstract: The invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organized by the byte in rows and columns, each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line through a selection element of the byte switch type, and each cell being connected to a respective control column through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase.

Abstract: On a substrate, first and second electrical connecting elements of an integrated circuit are disposed next to one another along a first direction. The first electrical connecting element is at a first distance from the second electrical connecting element. First and interconnects are disposed on the substrate, the first interconnect being connected to the first electrical connecting element and the second interconnect being connected to the second electrical connecting element. Third and fourth electrical connecting elements are disposed on the substrate and the first and second interconnects are disposed between the third and fourth electrical connecting elements and therebetween are at a second distance from one another, the second distance being smaller than the first distance.

Abstract: In a semiconductor device including a semiconductor wafer having a main surface where a circuit element is formed, electrode pads are formed at an upper portion of the main surface of the semiconductor wafer as electrically connected with the circuit element. A sealing resin seals the upper portion of the main surface of the semiconductor wafer, and external connection terminals are formed at the upper portion of the main surface so as to project out from the surface of the sealing resin and are arrayed in a substantially regular pattern over specific intervals from one another. At least one of the external connection terminals has a shape different from the shape of the other external connection terminals. The shape of the external connection terminal is used as an index mark, so that the index mark forming process is simplified and the index mark does not come off.

Abstract: According to a disclosed embodiment, a gas is supplied at a certain partial pressure for a chemical reaction with a top surface of a base in a transistor. The top surface of the base is heated to a certain temperature to promote the chemical reaction. For example, the gas can be oxygen, the base can be an epitaxial single crystal silicon-germanium base of a heterojunction bipolar transistor (“HBT”), and the chemical reaction can be oxidation of the silicon in the top surface of the silicon-germanium base. In one embodiment of the invention, the partial pressure of oxygen is maintained at 0.1 atmosphere and the top surface of the base is heated using rapid thermal processing (“RTP”) to a temperature of 500° C. The chemical reaction forms a dielectric layer on the top surface of the base. For example, using oxygen as stated above, a dielectric layer of silicon oxide (“interfacial oxide”) is formed.

Abstract: A SJ-LDMOST device offers significantly improved on-state, off-state, and switching characteristics of lateral power devices for power integrated circuits applications. The device is fabricated on an insulator substrate. The proposed structure achieves charge compensation in the drift region by terminating the bottom of the SJ structure by a dielectric hence eliminating the undesirable vertical electric field component and preventing any substrate-assisted-depletion. The device structural arrangement thereby achieve a uniform distribution of the electric field thus maximizing the BV for a given drift region length.

Abstract: A static random access memory cell comprising a first invertor including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup transistor; a second invertor including a second p-channel pullup transistor, and a second n-channel pulldown transistor in series with the second n-channel pullup transistor, the first invertor being cross-coupled with the second invertor, the first and second pullup transistors sharing a common active area; a first access transistor having an active terminal connected to the first invertor; a second access transistor having an active terminal connected to the second invertor; and an isolator isolating the first pullup transistor from the second pullup transistor.

Abstract: One aspect of the present invention relates to a system and method for improving memory retention in flash memory devices. Retention characteristics may be enhanced by nitridating the bottom silicon dioxide layer of the ONO dielectric. To further mitigate charge leakage within the memory cell, the charge retention layer, or silicon nitride layer of the ONO dielectric, may be passivated via a hydrogen anneal process in order to reduce the number of charge traps, and thus, the amount of charge loss. The present invention also provides a monitoring and feedback-relay system to automatically control ONO formation such that a desired ONO dielectric stack is obtained. The present invention may be accomplished in part by employing a measurement system to measure properties and characteristics of the ONO stack during the critical formation steps of the bottom silicon dioxide layer and a silicon nitride layer.

Abstract: A ferromagnetic thin-film based digital memory cell with a memory film of an anisotropic ferromagnetic material and with a source layer positioned on one side thereof so that a majority of conduction electrons passing therefrom have a selected spin orientation to be capable of reorienting the magnetization of the film. A disruption layer is positioned on the other side of the memory film so that conduction electrons spins passing therefrom are substantially random in orientation. The magnitude of currents needed to operate the cell can be reduced using coincident thermal pulses to raise the cell temperature.

Abstract: When a thin-film transistor (TFT) is formed on a glass substrate, electric charges caused in the TFT can be removed so as to avoid electrostatic damage in the TFT. A short-circuiting pattern that short-circuits the source region and the drain region of the TFT is added to a polysilicon pattern that constitutes the TFT. This short-circuiting pattern is removed at the same time as or after the wiring formation in the source region and the drain region.

Abstract: A non-volatile memory compatible with logic devices and processes is described. The non-volatile memory has a substrate, a first dielectric layer, a first gate, a second gate, a second dielectric layer, a plurality of spacers and a source/drain. A first active region and a second active region are formed on the substrate. When hot carrier effect occurs near the drain, the second dielectric layer located under the spacers is able to retain electrons so that the non-volatile memory is programmed.

Abstract: An active negative differential resistance element (an NDR FET) and a memory device (such as an SRAM) using such elements is disclosed. Soft error rate (SER) performance for NDR FETs and such memory devices are enhanced by adjusting a location of charge traps in a charge trapping layer that is responsible for effectuating an NDR behavior. Both an SER and a switching speed performance characteristic can be tailored by suitable placement of the charge traps.