Abstract: In order to prevent silicides from getting under side walls when the silicides are formed over MOSFET formed over an SOI substrate, trenches are defined in the SOI substrate and side walls are formed over the trenches, whereby the silicides are blocked so as not to get under a gate insulator with a lower portion of each side wall as a structure convex in a downward direction of the substrate. Thus, an increase in gate withstand voltage, a decrease in gate leakage current and control on a short channel effect are achieved.

Abstract: Disclosed is a method of horizontally growing carbon nanotubes, in which the carbon nanotubes can be selectively grown in a horizontal direction at specific locations of a substrate having catalyst formed thereat, so that the method can be usefully utilized in fabricating nano-devices. The method includes the steps of: (a) forming a predetermined catalyst pattern on a first substrate; (b) forming a vertical growth preventing layer on the first substrate, which prevents carbon nanotubes from growing in a vertical direction; (c) forming apertures through the vertical growth preventing layer and the first substrate to expose the catalyst pattern through the apertures; and (d) synthesizing carbon nanotubes at exposed surfaces of the catalyst pattern in order to grow the carbon nanotubes in the horizontal direction.

Abstract: An n-type layer of the opposite conduction type composed of n-GaN is formed between a light emitting layer and a p-type cladding layer composed of p-AlGaN. The bandgap of the n-type layer of the opposite conduction type is larger than the bandgap of the light emitting layer and is smaller than the bandgap of the p-type cladding layer.

Abstract: The bottom and the sides of a lower part of recess formed in the substrate has an insulating structure. A first part of the conductive structure of a first electric conductivity type is located in the lower part of the recess. A second part of the conductive structure of a second electric conductivity type, lower than the first type, is located in an upper part and borders the region of the substrate at the sides of the recess. The conductive structure has a diffusion barrier between its first and second parts. The conductive structure is configured as a bit line of a DRAM cell configuration with a vertical transistor, whereby S/Du represents the lower source/drain area and S/Do represents the upper source/drain area connected to a memory capacitor. Or, the conductive structure is configured as a memory capacitor and the upper source drain/area is connected to a bit line.

Abstract: In one embodiment, a process for fabricating a high-K layer comprising the steps of: placing a semiconductor substrate into a first chamber of a deposition apparatus; supplying high-K precursors to the deposition apparatus; generating ions or molecules of high-K material from the high-K precursors in a second chamber of the deposition apparatus, the second chamber being remote from the first chamber; passing the ions or molecules of high-K material from the second chamber to the first chamber; and depositing a high-K layer upon the semiconductor substrate.

Abstract: A structure that includes a substrate, typically a semiconductor chip such as a VCSEL or photodetector chip, and a guide for aligning a signal conveying device, typically an optical fiber, to a transducer such as an optoelectronic device on the semiconductor chip. The guide is formed, in a preferred embodiment, by lithographically exposing and developing a thick layer of photoresist. The structure is assembled by placing and securing the signal conveying device into a cavity-like region of the guide.

Abstract: The invention relates to a method of forming a quantum dot. A particle that includes a semiconductor material Y selected from the group consisting of Si and Ge is provided. Sound energy and light energy is applied to the particle to form a quantum dot. The quantum dot exhibits photoluminescence with a quantum efficiency that is greater than 10 percent. The quantum dot includes a core, and the core includes Y.

Abstract: A finger SQUID qubit device and method for performing quantum computation with said device is disclosed. A finger SQUID qubit device includes a superconducting loop and one or more superconducting fingers, wherein the fingers extend to the interior of said loop. Each finger has a mesoscopic island at the tip, separated from the rest of the finger by a Josephson junction. A system for performing quantum computation with the finger SQUID qubit device includes a mechanism for initializing, entangling, and reading out the qubits. The mechanism may involve passing a bias current across the leads of the superconducting loop and a mechanism for measuring a potential change across the leads of the superconducting loop. Furthermore, a control system includes a mechanism for addressing specific qubits in a quantum register of finger SQUID devices.

Abstract: An optoelectronic device and a method of manufacturing the same which the optoelectronic effect such as light emission or light reception can be increased by forming a dual-structural nano dot to enhance the confinement density of electrons and holes are provided. The optoelectronic device comprises an electron injection layer, a nano dot, and a hole injection layer. The nano dot has a dual structure composed of an external nano dot and an internal dot. The method of manufacturing the optoelectronic device comprises the steps of forming an electron injection layer on a semiconductor substrate; growing nano dot layer on the electron injection layer by an epi-growth method; heating the nano dot layer so that the nano dot has a dual structure composed of an external nano dot and an internal nano dot; and forming a hole injection layer on the overall structure.

Abstract: Semiconductor optoelectronic devices such as diode lasers are formed on GaAs with an active region with a GaAsN electron quantum well layer and a GaAsSb hole quantum well layer which form a type II quantum well. The active region may be incorporated in various devices to provide light emission at relatively long wavelengths, including light emitting diodes, amplifiers, surface emitting lasers and edge-emitting lasers.

Abstract: A thin film semiconductor transistor structure has a substrate with a dielectric surface, and an active layer made of a semiconductor thin film exhibiting a crystallinity as equivalent to the single-crystalline. To fabricate the transistor, the semiconductor thin film is formed on the substrate, which film includes a mixture of a plurality of crystals which may be columnar crystals and/or capillary crystal substantially parallel to the substrate. The resultant structure is then subject to thermal oxidation in a chosen atmosphere containing halogen, thereby removing away any metallic element as contained in the film. This may enable formation of a mono-domain region in which the individual columnar or capillary crystal is in contact with any adjacent crystals and which is capable of being substantially deemed to be a single-crystalline region without presence or inclusion of any crystal grain boundaries therein. This region is for use in forming the active layer of the transistor.

Abstract: A system for coupling optoelectronic devices, associated electrical components, and optical fibers is described. The system includes a substrate to which optoelectronic devices and at least some of the associated electronic components are formed on or formed using the substrate material. The substrate is further configured to receive and attach to one or more optical fibers. The system can be used to form transceivers for multiplexing and/or demultiplexing electronic information.

Abstract: An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well layer, an undoped SiGe spacer layer and a doped SiGe supply layer. The photodetector may be a metal-semiconductor-metal (MSM) or a p-i-n device. The detector may be integrated with an n- or p-type MODFET, or both in a CMOS configuration, and the MODFET can incorporate a Schottky or insulating gate. The invention overcomes the problem of producing Si-manufacturing-compatible monolithic high-speed optoelectronic circuits for 850 nm operation by using epixially-grown Si/SiGe heterostructure layers.

Abstract: A capacitive type MEMS switch having a conductor arrangement comprised of first and second RF conductors deposited on a substrate. A bridge member having a central enlarged portion is positioned over the conductor arrangement. In one embodiment, the first RF conductor has an end defining an open area in which is positioned a pull down electrode, with the end of the first RF conductor substantially surrounding the pull down electrode. In another embodiment, two opposed RF conductors, each having ends with first and second branches, define an open area in which a pull down electrode is positioned. A dielectric layer is deposited on the conductor arrangement such that when a pull down voltage is applied to the pull down electrode, the switch impedance is significantly reduced so as to allow signal propagation between the RF conductors.

Abstract: The present invention provides a method for forming an antifuse via structure. The antifuse via structures comprising a substrate that having a first conductive wire therein. Then, a first dielectric layer is formed on the substrate, and a photoresist layer is formed on the first dielectric layer. Next, an etching process is performed to etch the first dielectric layer to form a via open in the first dielectric layer. Then, a first conductive layer is deposited to fill the via open and performing a polishing process to form a conductive plug, wherein the conductive plug is on the first conductive wire. Next, a buffer layer deposited on the partial first dielectric layer and on the surface of conductive plug. Then, another polishing process is performed to the buffer layer to expose the portion of the conductive plug. Thereafter, a first electrode of capacitor is deposited on the buffer layer.

Abstract: The present invention comprises: a plurality of output terminals through which a signal from an internal circuit is output; buffer circuits, each provided between one of the plurality of output terminals and the internal circuit; and a delay circuit connected to the specific buffer, the delay circuit delaying the signal from the internal circuit. With this arrangement, it is possible to measure a delay time from an input test signal even when a super-high-speed device is tested.

Abstract: A II-VI semiconductor device includes a stack of II-VI semiconductor layers electrically connected to a top electrical contact. A GaAs substrate is provided which supports the stack of II-VI semiconductor layers and is positioned opposite to the top electrical contacts. A BeTe buffer layer is provided between the GaAs substrate and the stack of II-VI semiconductor layers. The BeTe buffer layer reduces stacking fault defects at the interface between the GaAs substrate and the stack of II-VI semiconductor layers.

Abstract: A monolithic surface mount optoelectronic device includes a transparent epoxy layer and a glass layer, which cover the active surface of a light emitting diode junction. The diode junction preferably outputs a characteristic wavelength of about 450 nm (blue light). The junction is fabricated by growing a P+ layer, gallium nitride layer, and a silicon gallium nitride buffer layer on a silicon substrate. The buffer layer, which is preferably non-conductive, is made conductive by the addition of a metallic shorting ring connecting the gallium nitride layer through a via in the silicon substrate to one of two surface mount contacts. A conductive beam connects the P+ layer to the remaining surface mount contact through another via in the silicon substrate. An isolation trench separates the vias in the substrate.

Abstract: A magnetic tunnel junction (MTJ) sensor system and a method for fabricating the same are provided. First provided are a first lead layer, and a pinned layer. Positioned adjacent to pinned layer is a free layer. The magnetization direction of the pinned layer is substantially perpendicular to the magnetization direction of the free layer at zero applied magnetic field. Also included is a tunnel barrier layer positioned between the pinned layer and the free layer. Further provided is a second lead layer, where the pinned layer, the free layer, and the tunnel barrier layer are positioned between the first lead layer and the second lead layer. A pair of hard bias layers are positioned adjacent to the pinned layer, the free layer, and the tunnel barrier layer. To prevent shunt currents from flowing, insulating layers are positioned between the hard bias layers and the first lead layer and the second lead layer. Such insulating layers are constructed from a non-conductive, magnetic material.

Abstract: A MOSFET gate electrode is interrupted from extending across a common conduction region, thereby reducing gate capacitance. The reduced gate capacitance provides very low gate-to-drain charge, QGD, and very low gate-to-source charge, QGS. The gate electrode is supported by and is in effect or is actually interrupted by an oxide block over a common conduction area. The MOSFET can be formed by methods including: patterning oxide blocks on a substrate; providing gate electrode material in and over appropriate gaps between the oxide blocks; removing excess gate material; and forming oxide layers around the gate electrode material. Oxide blocks can alternately be patterned to permit gate electrodes to be formed directly between the oxide blocks. The reduced gate capacitance reduces switching delays while permitting minimum RDSON values.