Abstract: In a method of dicing a wafer, which comprises a plurality of individual circuit structures, a trench is first defined between at least two circuit structures on one face of the wafer. Subsequently, the trench is deepened down to a defined depth. Following this, one face of the wafer has fixed thereto a re-detachable intermediate support composed of a fixed intermediate support substrate and an adhesive medium which is applied to said intermediate support substrate and which can specifically be modified in terms of its adhesive strength, whereupon the wafer is dry-etched from the opposite face so that circuit chips are obtained which are connected to one another only via the intermediate support. Subsequently, the circuit chips are removed from the intermediate support.

Abstract: The present invention discloses an optical-fiber-block assembly for minimizing stress concentration. The optical-fiber-block assembly is comprised of a fiber-alignment area mounted with a plurality of V-grooves at which optical fibers are disposed and a stress-relief-depth area extending from the fiber-alignment area and formed by etching the fiber-alignment area deeper by a predetermined amount, for relieving stress that is caused by the coating thickness of the fiber, wherein the fiber-alignment area further includes: (a) a first fiber-alignment area having a first V-grooves with a constant width for receiving the bare fibers, such that the first fiber-alignment area do not contact the external side of the bare fiber, and (b) a second fiber-alignment area having a second V-grooves with a constant width extending from the first V-grooves for receiving the bare fiber, wherein the width of the first V-grooves is substantially wider than the width of the second V-grooves.

Abstract: A semiconductor device which has satisfactory characteristics is provided. The semiconductor device includes a TFT manufactured by using a satisfactory crystalline semiconductor film and a circuit manufactured by using the TFT. An n-type impurity element (typically, phosphorous) is added to a gettering region of an n-channel TFT. A p-type impurity element (typically, boron) and a rare gas element (typically, argon) are added to a gettering region of a p-channel TFT. Then, there is performed heat treatment for gettering a catalytic element that remains in a semiconductor film.

Abstract: A distributed photodiode structure is shown formed on a semiconductor substrate having a first dopant type where a first plurality of diffusions of a second dopant type are formed on a first surface of the substrate. A second plurality of diffusions having the first dopant type are formed on the first surface of the substrate between the first plurality of diffusions. In a further refinement, a second surface of the substrate is diffused with the first dopant type. In yet another refinement, a plurality of trenches are formed on the first surface and the second plurality of diffusions are formed within the trenches.

Abstract: A method of creating a hybridized chip using a top active optical device combined with an electronic chip having electronic chip contacts, when at least some of the active device contacts are not aligned with at least some of the electronic chip contacts, each of the at least some active device contacts having an electrically corresponding electronic chip contact. The method involves creating sidewalls defining openings in the substrate, extending from the first side at the active device contacts to a bottom of the substrate opposite the first side, at points substantially coincident with the active device contacts; making the sidewalls electrically conductive; and connecting the points and the electronic chip contacts with an electrically conductive material. A hybridized chip has at least one top active optical device coupled to an electronic chip, the hybridized chip having been created using a described method.

Abstract: A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises forming a planar-surfaced layer of material, having a first index of refraction, over a substrate of the semiconductor device, assembly or laminate. A corrective layer is formed over the planar-surfaced layer and a second layer, having a second index of refraction, is then formed over the corrective layer. The corrective layer is composed of a material having an intermediate index of refraction between the first index of refraction and the second index of refraction. The method can also be modified to include one or more layers of materials and/or intermediate refraction layers interposed between or above any of the aforementioned adjacent layers.

Abstract: A silicon-germanium hetero bipolar transistor comprising a silicon collector layer, a boron-doped silicon-germanium base layer, a silicon emitter layer and an emitter contact area. The transistor is fabricated using an epitaxy process on a surface of pure silicon. An electrically inert material is incorporated into the epitaxial layers in order to link the defects in the semiconductor structure and to reduce the outdiffusion of the dopant. Thus, a transistor for high-frequency applications can be fabricated in two ways: to increase the dopant dose of the base region or to reduce the thickness of the base layer. In particular, carbon is incorporated in the base layer and in the collector layer and/or emitter layer.

Abstract: The semiconductor device according to the present invention comprises a V-groove having V-shaped cross-section formed on a semiconductor substrate or on an epitaxial growth layer grown on a semiconductor substrate, and an active layer is provided only at the bottom of said V-groove. The method for manufacturing a semiconductor device according to the present invention comprises the steps of forming a stripe-like etching protective film in <011> direction of a semiconductor substrate or an epitaxial growth layer grown on it, performing gas etching using hydrogen chloride as etching gas on a semiconductor substrate or on an epitaxial growth layer grown on a semiconductor substrate to form a V-groove, and forming an active layer at the bottom of said V-groove.

Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.

Abstract: A field effect transistor having a variable doping profile is presented. The field effect transistor is integrated on a semiconductor substrate with a respective active area of the substrate including a source and drain region. A channel region is interposed between the source and drain regions and has a predefined nominal width. The effective width of the channel region is defined by a variable doping profile.

Abstract: A current measurement circuit and method for testing a semiconductor device is provided. The method includes the steps of providing a semiconductor integrated circuit device including a voltage regulating circuit, the voltage regulating circuit being activated as needed to maintain a required voltage level; monitoring the voltage regulating circuit to determine a number of times it is activated during a sample period; and comparing the number of activations to a predetermined limit whereby if the number of activations exceeds the predetermined limit the semiconductor device is defective. The current measurement circuit includes an external clock for providing a clock signal; a first counter for counting when the voltage regulating circuit is activated; a second counter for counting clock cycles of a sample period; and a register for storing the number of activations, wherein the number of activations represents a relative current consumption value of the semiconductor device.

Abstract: A reflector that functions as a fluorescent member is formed of a transparent resin material including a fluorescent substance dispersed therein capable of emitting light by excitation of light emitted from a semiconductor light emitting element, on the bottom of the case so as to surround the semiconductor light emitting element, having an inner surface of curved surface of concave arc shape having a section extending from the height of the bottom of the case obliquely upward, in a shape that continues along substantially the entire circumference of an oval or elongated round shape, thereby achieving uniform light emission without color heterogeneity, for example, white light of high output power.

Abstract: An electrode pad for a Group III nitride compound semiconductor having p-type conduction includes a triple layer structure having first, second, and third metal layers, formed on an electrode layer. A protection film with a window exposing a central portion of the third metal layer is formed by etching on the third metal layer and covers the sides of the first, second, and third metal layers. The second metal layer is made of gold (Au). The first metal layer is made of an element which has ionization potential lower than gold (Au). The third metal is made of an element which has adhesiveness to the protection film stronger than that of gold (Au). Consequently, this structure of the electrode pad improves the adhesive strength between the protection layer and the third meal layer and prevents the etching of the sides of the protection film. Furthermore, the contact resistance between the semiconductor and the electrode pad is lowered and, thus, ohmic characteristic of the electrode pad is improved.

Abstract: A triplet light emitting device which has high efficiency and improved stability and which can be fabricated by a simpler process is provided by simplifying the device structure and avoiding use of an unstable material. In a multilayer device structure using no hole blocking layer conventionally used in a triplet light emitting device, that is, a device structure in which on a substrate, there are formed an anode, a hole transporting layer constituted by a hole transporting material, an electron transporting and light emitting layer constituted by an electron transporting material and a dopant capable of triplet light emission, and a cathode, which are laminated in the stated order, the combination of the hole transporting material and the electron transporting material and the combination of the electron transporting material and the dopant material are optimized.

Abstract: A semiconductor device is disclosed and includes a drain region of a first conductivity type, having a first major surface. Diffused into the drain region is a body region of a second conductivity type. A source region is diffused in the body region and it has a general polygonal shape when viewed at the first major surface with two notches directed towards the center of the source region from opposite sides. The body region is accessible through the notches. An oxide layer covers the source and body regions except for a contact opening position over the source region between the two notches exposing only that portion of the source region that is between the two notches and at least a portion of the accessible body region in each of the two notches to facilitate a source contact.

Abstract: A memory element with organic material comprises two metallized layers, arranged one on top of the other, with first lines and second lines which are arranged to intersect with each other. A channel is formed at the intersections between the first line and the second line, which overlaps the first line partially and completely overlaps the second line. The channels are filled with a filling material, the electrical conductivity of which may be altered by an applied electrical voltage.

Abstract: It is intended to provide multi-piece circuit boards capable of preventing lowering of strength of joint sections between piece sections after cutoff and other sections, and determining material of flame sections regardless of material of a piece section, and board manufacturing method of such multi-piece circuit boards. For a mixed board including a defective piece section and a good piece section in a state in which an outermost layer is not formed yet, cut lines are made around bridges and are joined together by adhesive, and an upper layer is provided thereon, whereby a multi-piece circuit board mounted on good piece sections only is formed. A frame section may be formed by arranging respective piece sections manufactured in advance at positions at which the piece sections are to be present and injecting fluid matter to surround the respective piece sections arranged to form the frame section.

Abstract: Improved resonant reflectors are provided for increased mode control of optoelectronic devices. Some of the resonant reflectors provide improved mode control while not requiring significant additional processing steps, making them ideal for commercial applications. Other resonant reflectors reduce or eliminate abrupt changes in the reflectively of the resonant reflector across an optical cavity of an optoelectronic device, allowing them to reduce or eliminate undesirable diffraction effects that are common in many resonant reflectors.

Abstract: An improved optical interconnect structure, system including the structure, and method of forming the structure and system are disclosed. The optical interconnect structure includes a waveguide and a reflective structure. Either the waveguide, the reflective structure, or both include a curved surface to facilitate focusing of light transmitted between the waveguide and an optoelectronic device.

Abstract: In an SRAM, memory cells are each constructed of four NMOS transistors and two PMOS transistors 25 and 26. The four NMOS transistors are each constructed of DTMOS in which the channel region is electrically connected to the gate. In each NMOS transistor, a threshold voltage Vth is lower in an ON stage than in an OFF stage. The threshold voltage Vth in the OFF stage is equivalent to that of an ordinary NMOS transistor in which the channel region is not electrically connected to the gate. Read and write circuits of the SRAM also include MOS transistors formed of DTMOS in which the channel region is electrically connected to the gate.