Abstract: Various embodiments comprise methods and related apparatuses formed from those methods for placing at least portions of peripheral circuits under a DRAM memory array, where the peripheral circuits are used to control an operation of the DRAM memory array. In an embodiment, a memory apparatus includes a DRAM memory array and at least one peripheral circuit formed under the DRAM memory array, where the at least one peripheral circuit includes at least one circuit type selected from sense amplifiers and sub-word line drivers. Additional apparatuses and methods are also disclosed.

Abstract: Methods, systems, and devices for operating memory cell(s) are described. A resistance of a storage element included in a memory cell may be programmed by applying a voltage to the memory cell that causes ion movement within the storage element, where the storage element remains in a single phase and has different resistivity based on a location of the ions within the storage element. In some cases, multiple of such storage elements may be included in a memory cell, where ions within the storage elements respond differently to electric pulses, and a non-binary logic value may be stored in the memory cell by applying a series of voltages or currents to the memory cell.

Abstract: A semiconductor circuit according to the disclosure includes a first circuit that can generate an inverted voltage of a voltage at a first-node and apply the inverted voltage to a second-node, a second circuit that can generate an inverted voltage of the voltage at the second-node and apply the inverted voltage to the first-node, a first transistor coupling the first-node to the third-node by turning on, a first storage element having a first terminal coupled to the third-node and a second terminal supplied with a control voltage and being able to take a first or second resistance state, a first voltage setting circuit that is coupled to the third-node and can set a voltage at the third-node to a voltage corresponding to a voltage at a predetermined node out of the first and second nodes, and a driver controlling an operation of the first transistor and setting the control voltage.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device to program a selected physical page of the semiconductor memory device. The method may include performing a plurality of program loops. Each of the program loops may include: applying a bit line voltage based on data input to a page buffer of the semiconductor memory device; applying a two-step program pulse to a word line coupled to the selected physical page; performing a program verify operation on the selected physical page using a double verify scheme; and determining a bit line voltage to be applied in a subsequent program loop based on a result of the program verify operation.

Abstract: The present disclosure relates to a non-volatile memory and operating method thereof. The non-volatile memory includes multiple memory strings, multiple bit switch units, a memory operation circuit and multiple source switch units. The bit switch units are electrically connected to the memory strings. The memory operation circuit is electrically connected to the bit switch units to transmit a write signal to the memory unit strings. The source switch units are electrically connected to the memory string so that the memory strings receive a bias signal via the source switch unit. In a program mode, when a first bit switch unit of the bit switch units is turned on and a first memory strings receives the write signal through the first bit switch unit, the source switch units electrically connected to the other memory strings will be turned on.

Abstract: A memory device includes a plurality of memory cells, a plurality of word lines, and a word line driver. The word lines are respectively coupled to the memory cells. The word line driver is configured to respectively drive the word lines with word line signals that have varying pulse widths.

Abstract: An electronic device applicable to an artificial neuron network. The electronic device includes a first circuit, a second circuit, and first to sixth wirings. The first circuit includes a first transistor, a second transistor, and a capacitor. The second circuit includes a third transistor. A gate of the third transistor is electrically connected to the third wiring. The capacitor capacitively couples the third wiring and the gate of the second transistor. The first circuit is capable of storing a weight as an analog value. The first transistor is typically an oxide semiconductor transistor.

Abstract: A memory controller may detect degradation in accordance with a bit error rate (BER) of the resistive memory device including memory cells. The memory controller may control the memory cells to be programmed to a first resistance state, read the programmed memory cells, and receive the BER of the memory cells generated during a read operation from the resistive memory device. The memory controller may determine a quantity of program cycles of the memory cells based on the BER. The quantity may be determined based on reference to a lookup table indicating a correlation between the BER and the quantity of program cycles.

Abstract: A bias circuit includes a charging current reproduce unit, a cell current reproduce unit, a current comparator, and a bit line bias generator. The charging current reproduce unit generates a charging reference voltage according to a charging current flowing through a voltage bias transistor. The cell current reproduce unit generates a cell reference voltage according to a cell current flowing through a common source transistor. The current comparator includes a first current generator for generating a replica charging current according to the charging reference voltage, and a second current generator for generating a replica cell current according to the cell reference voltage. The bit line bias generator generates a bit line bias voltage to control a page buffer for charging a bit line according to a difference between the replica charging current and the replica cell current.

Abstract: A method for detecting unreliable bits in transistor circuitry includes applying a controllable physical parameter to a transistor circuitry, thereby causing a variation in a digital code of a cryptologic element in the transistor circuitry, the variation being a tilt or bias in a positive or negative direction. An amount of variation in the digital code of the cryptologic element is determined. Unreliable bits in the transistor circuitry are defined as those bits for which the variation is in a range defined as unreliable.

Abstract: Magnetoelectric or magnetoresistive memory cells include at least one of a high dielectric constant dielectric capping layer and/or a nonmagnetic metal dust layer located between the free layer and the dielectric capping layer.

Abstract: An integrated circuit includes: one or more first sections in which first to Nth data (where N is an integer equal to or greater than 2) corresponding to one command are transferred through one line; and two or more second sections in which the first to Nth data are serial-to-parallel converted in 1:N and transferred through N lines, wherein whenever the command is applied, the first to Nth data are transferred without being inverted or transferred after being inverted repeatedly in at least one second section among the two or more second sections.

Abstract: Memory devices, memory systems, and systems, include memory devices with a bonding pad region for coupling command-and-address (CA) input signals and a memory cell region for storing information in memory cells. A centralized CA interface region includes input circuits coupled to the CA input signals. At least two of the input circuits are configured in pairs. Each pair includes a first input circuit coupled to a first input and configured to generate a first output and a second input circuit coupled to a second input and configured to generate a second output. Each pair also includes a swap circuit disposed between the first input circuit and the second input circuit. The swap circuit selects one of the first output or the second output for a first internal signal and selects the other of the first output and the second output for a second internal signal responsive to a control signal.

Abstract: Disclosed is a three-dimensional non-volatile ferroelectric memory including a ferroelectric memory array structure, wherein the ferroelectric memory array structure includes multiple layers of ferroelectric memory cell array disposed in a stacked way, and each layer of the ferroelectric memory cell array includes ferroelectric memory cells arranged in rows and columns; wherein word lines and bit lines which are substantially orthogonal to each other are oppositely disposed on two sides of the corresponding ferroelectric memory cell respectively, and a reference ferroelectric body is disposed adjacent to the corresponding ferroelectric memory cell. A polarization direction of an electric domain in the ferroelectric memory cell is not perpendicular to an electric field direction of a write voltage signal applied to the word line and the bit line; and when the write voltage signal is applied between the word line and the bit line.

Abstract: A semiconductor storage device includes first, second, and third transistors, first, second, and third bit lines connected to the first, second, and third transistors, a word line connected to the first, second, and third transistors, and a control circuit configured to perform a program operation for writing data to the second and third transistors, including raising a first voltage applied to the first bit line at a first timing, raising a second voltage applied to the word line at a second timing, raising a third voltage applied to the second bit line at a third timing, raising a fourth voltage applied to the third bit line at a fourth timing, and lowering the first voltage at a fifth timing. The first voltage is raised to a first predetermined voltage, and each of the third and fourth voltages is raised to a second predetermined voltage smaller than the first predetermined voltage.

Abstract: A resistive memory device according to an example embodiment of the inventive concepts includes: a cell array including a first section and a second section; a first column switch circuit connected to a memory cell and a reference cell of the first section through first bit lines; a second column switch circuit connected to a memory cell and a reference cell of the second section through second bit lines; and a column decoder configured to control the first and second column switch circuits such that one of the first bit lines connected to the memory cell and one of the second bit lines connected to the reference cell are selected according to a first column address, and one of the first bit lines connected to the reference cell and one of the second bit lines connected to the memory cell are selected according to a second column address.

Abstract: A circuit includes: a first node to receive a first current; a first resistive element receiving a first branch current of the first current; first transistors each including a first terminal connected to the second end of the first resistive element; a second resistive element connected to the first node and receiving a second branch current of the first current; a second node to receive a second current; a second transistor including a first terminal, the first terminal of the second transistor connected to the second node and receiving a first branch current of the second current; a third resistive element connected to the second node and receiving a second branch current of the second current; wherein a temperature coefficient is adjusted by a resistance of the second resistive element and a resistance of the third resistive element and corresponding to the first current.

Abstract: First and second memory cell arrays each having memory cells arranged in the X and Y directions lie side by side in the Y direction with space between them. A relay buffer is provided between first and second row decoders for buffering a control signal to be supplied to the second row decoder. An inter-array block between the first and second memory cell arrays is constituted by at least either a tap cell or a dummy memory cell. The relay buffer and the inter-array block are the same in position and size in the Y direction.

Abstract: A memory device includes a memory cell array, a write/read circuit, a control circuit and an anti-fuse array. The memory cell array includes a plurality of nonvolatile memory cells. The write/read circuit performs a write operation to write write data in a target page of the memory cell array, verifies the write operation by comparing read data read from the target page with the write data and outputs a pass/fail signal indicating one of a pass or a fail of the write operation based on a result of the comparing. The control circuit controls the write/read circuit and selectively outputs an access address of the target page as a fail address in response to the pass/fail signal. The anti-fuse array in which the fail address is programmed, outputs a repair address that replaces the fail address.

Abstract: A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit including an input for receiving a power loss signal in response to a power loss from at least one power source, an input configured to receive data from a volatile memory, a single block of non-volatile matrix of memory cells and a driver circuit coupled to said single row of non-volatile matrix of memory cells. The driver circuit is configured to write data to and read data from said single block of non-volatile matrix of memory cells. The single block of non-volatile matrix of memory cells can be provided as a single row electrically erasable programmable read only memory (EEPROM).