Abstract: Disclosed is a method, a system, and a user interface for determining a preferred relative arrangement of digital restoration designs and digital representations of multi-shaded milling blocks for use when manufacturing dental restorations from multi-shaded milling blocks. A preferred first relative arrangement of a first digital restoration design and a digital representation of a first multi-shaded milling block is determined, and therefrom a preferred second relative arrangement of a second digital restoration design and a digital representation of a second multi-shaded milling block is determined.

Abstract: A neuromorphic memory system including neuromorphic memory arrays. The neuromorphic memory system includes a presynaptic neuron circuit coupled to a postsynaptic neuron circuit by a resistive memory cell. The method includes generating a presynaptic LIF pulse on a presynaptic LIF line at time t1. An activating operation activates an access transistor coupled to the presynaptic LIF line in response to the presynaptic LIF pulse. The access transistor enables LIF current to pass through the resistive memory cell to a postsynaptic LIF line. An integrating operation integrates the LIF current at the postsynaptic LIF line over time. A comparing operation compares a LIF voltage at the postsynaptic LIF line to a threshold voltage. A generating operation generates a postsynaptic spike timing dependent plasticity (STDP) pulse on a postsynaptic STDP line if the LIF voltage is beyond the threshold voltage.

Abstract: A method for detecting a flash memory array includes a plurality of word lines, a plurality of bit lines, and a source line, includes executing a first detection process. The first detection process includes: applying a first positive voltage to a P-type well of the flash memory array; applying a ground to all the word lines; floating the bit lines and the source line; determining whether a leakage current flowing through the P-type well exceeds a leakage threshold; and when the leakage current exceeds the leakage threshold, determining that at least one of the word lines is short-circuited with at least one of the bit lines or the source line.

Abstract: A 3D NAND array with divided string architecture. In one aspect, an apparatus includes a plurality of charge storing devices connected to form a cell string. The apparatus also includes one or more internal select gates connected between selected charge storing devices in the cell string. The one or more internal select gates divide the cell string into two or more segments of charge storing devices. Selectively enabling and disabling the one or more internal select gates during programming operates to isolate one or more selected segments to reduce program-disturb to remaining segments. In another embodiment, a method is provided for programming a memory cell of a cell string having internal select gates that isolate the memory cell to reduce the effects of program-disturb. In another embodiment, multiple memory cells of a cell string having internal select gates are programmed with reduced program-disturb.

Abstract: An integrated circuit including a ferroelectric random access memory (FRAM) for storing firmware, and a method of updating that firmware. The FRAM is constructed to selectively operate as a 2T2C FRAM memory in a normal operating mode, and as a 1T1C FRAM memory in an update mode. Updating of the stored firmware is performed by placing the FRAM in its update (1T1C) mode and writing the updated code into alternate rows of the 1T1C half-cells at each of a plurality of memory locations, while the other 1T1C half-cells in the other alternate rows retain the original data. Following verification of the updated contents, the original data in the other half-cells are overwritten with the verified updated data, and the operating mode is changed back to the normal (2T2C) operating mode.

Abstract: The present application provides a NAND flash memory, comprising: a control unit, which includes a signal receiving unit, a voltage boosted circuit and a flash array; and a power source supplying power to the control unit; wherein when the voltage boosted circuit receives an erase signal from the signal receiving unit, the voltage boosted circuit exerts a device erase pulse whose magnitude is larger than an initial voltage to blocks of the flash array to permanently erase data in the blocks; the blocks include power-on read blocks. By removing data from at least power-on read blocks, the present invention discloses a scheme for permanently destroying the NAND flash memory.

Abstract: A semiconductor device includes a read mode signal generation circuit and a read alignment circuit. The read mode signal generation circuit compares a read command with at least one of internal clock signal to generate a read mode signal. The read alignment circuit is synchronized with the at least one internal clock signal to generate read data in response to internal data. The read alignment circuit controls an alignment sequence of the internal data in response to the read mode signal.

Abstract: A mobile device and a method for estimation of direction of motion of a user are described. The mobile device comprises an inertial sensor to capture acceleration signals based on motion of the user and a direction estimation module. The direction estimation module determines direction of gravity based on filtering acceleration values obtained from captured the acceleration signals using a low-pass filter to identify a plane orthogonal to the direction of gravity. The plane orthogonal to the gravity comprises two orthogonal axes orthogonal to the direction of gravity. Further, displacement values are evaluated based on a user input for placement of the mobile device with respect to user's body, and integration of the acceleration values across the two orthogonal axes with respect to time. A direction of motion of the user is estimated based on a ratio of the displacement values along the two orthogonal axes.

Abstract: A memory device includes a plurality of memory cells, a plurality of word lines, and a word line driver. The word lines are respectively coupled to the memory cells. The word line driver is configured to respectively drive the word lines with word line signals that have varying pulse widths.

Abstract: Examples described include apparatuses and methods for determining stability of memory cells. Resistance variable memory cells may be used. Once a memory cell is placed in a low or high resistance state responsive to set or reset pulses, the stability of the state may be determined, such as by providing another pulse to the memory cell or otherwise stressing the cell. The another pulse may be of an opposite polarity to the set or reset pulses already applied. If the memory cell is no longer in the target state after providing the another pulse, additional set or reset pulses may be applied to achieve a stable state.

Abstract: A word-line controller applies a voltage to a selected word-line. A bit-line controller applies voltages to bit-lines. A detector detects data of memory-cells. A write sequence of writing data in selected memory-cells connected to the selected word-line has at least one write-loop including a write operation of applying a plurality of write voltages with the word-line controller and the bit-line controller, and a verify operation of verifying with the detection circuit whether a threshold voltage of each of the selected memory-cells has reached a plurality of reference voltages for corresponding write data. The word-line controller and the bit-line controller select a write voltage corresponding to a threshold voltage of each of the selected memory-cells from among the write voltages with respect to each of the write-loops, and apply the selected write voltage to the selected memory-cell in a subsequent write operation.

Abstract: A memory device that supports a built-in self-test (BIST) operation includes: a plurality of memory cells; a page buffer group including page buffer circuits respectively coupled to the plurality of memory cells through bit lines; a built-in self-test (BIST) controller configured to generate pattern data to be stored in the page buffer circuits and reference data to be compared with sensed data obtained from the page buffer circuits, and to compare the reference data with the sensed data; and an input/output control circuit configured to input the pattern data to the page buffer circuits and to transfer the sensed data from the page buffer circuits to the BIST controller.

Abstract: A voltage generator of a nonvolatile memory device includes a charging circuit, a current mirror circuit, a discharging circuit and an output circuit. The charging circuit amplifies a difference between a reference voltage and a feedback voltage to generate a first current. The current mirror circuit is connected to the charging circuit and generates a second current based on the first current. The discharging circuit is connected to the current mirror circuit to draw the second current, and discharges the output voltage to a target level by adjusting discharging amount of the second current based on a sensing voltage which reflects a change of the feedback voltage. The output circuit is connected to the current mirror circuit, and provides the output voltage based on the first current and the second current to a first word-line connected to an output node.

Abstract: A memory check ASIC for fuzes and safety and arming (S&A) devices. The memory check ASIC may comprise: an ASIC, data line, clock line, shutdown line, and reset line. The ASIC may operatively couple to a microcontroller having a flash-based memory and may comprise: a digital logic for verifying a calculated checksum based on contents of the flash-based memory. A clock signal along with the calculated checksum may be transmitted to the ASIC via the clock line and data line, respectively. A shutdown signal may be transmitted from the ASIC to the microcontroller via the shutdown line in response to the verification of the calculated checksum by the digital logic. A reset signal may synchronize sampling of the calculated checksum and may be latched by flip-flop circuits of the digital logic for a predetermined number of clock cycles.

Abstract: A system and method for non-invasive reconstruction of an entire object-specific or person-specific teeth row from just a set of photographs of the mouth region of an object (e.g., an animal) or a person (e.g., an actor or a patient) are provided. A teeth statistic model defining individual teeth in a teeth row can be developed. The teeth statistical model can jointly describe shape and pose variations per tooth, and as well as placement of the individual teeth in the teeth row. In some embodiments, the teeth statistic model can be trained using teeth information from 3D scan data of different sample subjects. The 3D scan data can be used to establish a database of teeth of various shapes and poses. Geometry information regarding the individual teeth can be extracted from the 3D scan data. The teeth statistic model can be trained using the geometry information regarding the individual teeth.

Abstract: Aspects of the disclosure provide magnetoresistive random access memory (MRAM) and methods. The MRAM generally includes a first magnetic tunnel junction (MTJ) storage element comprising a first fixed layer, a first insulating layer, and a first free layer, and a second MTJ storage element comprising a second fixed layer, a second insulating layer, and a second free layer. The MRAM further includes a conductive layer connected to a source line, first bit line, and a second bit line, wherein the first MTJ storage element is disposed above and connected to the conductive layer and the first bit line at a first end and connected to the first bit line at a second end, and wherein the second MTJ storage element is disposed above and connected to the conductive layer and the second bit line at a first end and connected to the second bit line at a second end.

Abstract: A memory system is provided. The memory system includes a memory device and a memory controller. The memory device includes a plurality of memory dies and a refresh controller, and the refresh controller includes a refresh skip control block. The memory controller transmits a refresh skip period signal of each of the memory dies to the refresh skip control block according to a result of an error correction code (ECC) decoding operation performed on each of the memory dies so that the memory dies have independent refresh skip periods.

Abstract: Static random access memories (SRAM) are provided. The SRAM includes a plurality of bit cells. Each bit cell includes a first inverter, a second inverter cross-coupled with the first inverter, a first pass gate transistor coupled between the first inverter and a bit line, and a second pass gate transistor coupled between the second inverter and a complementary bit line. The bit cells are divided into a plurality of top tier cells and a plurality of bottom tier cells, and each of the bottom tier cells is disposed under the individual top tier cell. The first inverter of the top tier cell is disposed on the second inverter of the corresponding bottom tier cell within a substrate, and the second inverter of the top tier cell is disposed on the first inverter of the corresponding bottom tier cell within the substrate.

Abstract: Several embodiments of memory devices and systems with walking read level calibration are disclosed herein. In one embodiment, a system includes a memory component having at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to perform iterative calibrations of the memory region by determining a first read level offset value during a first calibration. A new base read level test signal is determined based on the first read level offset value. During a second calibration using the new base read level test signal, a second read level offset value is determined.

Abstract: Provided herein may be a memory system and a method of operating the same. The method of operating a memory system may include receiving a first program command, and performing an operation corresponding to the first program command, receiving a second program command while performing the operation corresponding to the first program command, delaying setting of a queue status register for the second program command by a first wait time, receiving a third read command before the first wait time elapses, and setting the queue status register for the third read command before setting the queue status register for the second program command.