Patents Examined by Douglas W. Sergent
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Patent number: 6246975Abstract: A computer implemented simulation and evaluation method simulates interventions to a patient by a user, and evaluates the interventions responsive to predetermined criteria and the interventions. The method includes defining a test area to evaluate the user to at least one of predetermined criteria and a user profile, selecting genetic information of the patient responsive to the test area, and generating a patient history responsive to the test area and the genetic information. The method also includes receiving at least one intervention input by the user, and evaluating the user responsive to the intervention and predetermined criteria.Type: GrantFiled: October 30, 1997Date of Patent: June 12, 2001Assignee: American Board of Family Practice, Inc.Inventors: Richard J. Rivonelli, Walton Sumner, II, Victor W. Marek, Miroslaw Truszczynski
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Patent number: 6246974Abstract: A method of determining characteristics of a rotary drag-type drill bit comprises the steps of: creating a computerized representation of the cutters on the drill bit, and then, with each cutter in turn, projecting the shape of the cutter onto a fixed plane having an array of cells, and assigning a first marker to those cells of the array which overlie the projection of the selected cutter. The representations of the other cutters are then rotated about the bit axis until they have all passed through the plane at least once, the cutters also being moved axially while being rotated so as to represent the axial movement of the bit during drilling. The shapes of the other cutters are projected onto the plane, as they pass through it, and a second marker is assigned to those cells of the array which overlie both the projection of the selected cutter and the projections of any of the other cutters.Type: GrantFiled: September 24, 1998Date of Patent: June 12, 2001Assignee: Camco International (UK) LimitedInventors: David John Jelley, Nigel Shaun Wilcox
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Patent number: 6243665Abstract: The monitoring control apparatus according to the present invention performs a test on each integrated circuit that supports the boundary scan test method loaded on CPU board 4 and control board 5, and on the connection relationships of these integrated circuits, by a boundary scan controller board 7 like that shown, for example, in FIG. 1. If an abnormality is detected in CPU board 4 or control board 5, an alarm apparatus 9 is activated which emits an alarm. Moreover, if the type of abnormality is such that there is the risk of it having a significant effect on the operation of a robot 3, which is the target of this monitoring and control, from the viewpoint of safety, main power supply apparatus 6 of robot 3 is interrupted to prevent in advance robot 3 from running out of control.Type: GrantFiled: August 22, 1997Date of Patent: June 5, 2001Assignee: Duaxes CorporationInventors: Mitsugu Nagoya, Kazumi Sakamaki
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Patent number: 6243668Abstract: A method of executing a program compiled for a base instruction set architecture different than a native instruction set architecture, on a native machine by organizing a runtime system module into at least a low level domain, a medium level domain, and a high level domain. A memory buffer referred to as a backing store is created to correspond to a register stack and have a one-to-one mapping with the register stack. The invention initializes a beginning of the backing store to contain user-visible register values which constitute base instruction set architecture register values, and sets a virtual instruction pointer to a current instruction which is to be executed. The method of the present invention executes a start routine for forcing a reload of the user-visible register values from the backing store to the register stack and returns to the low level domain to perform a lookup operation in a translation lookaside buffer.Type: GrantFiled: August 7, 1998Date of Patent: June 5, 2001Assignee: Hewlett-Packard CompanyInventors: Bich-Cau Le, Anthony Fitzgerald Istvan
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Patent number: 6240377Abstract: An E2PROM controller is provided for an emulation chip. An E2PROM is connected to a CPU via a memory interconnect bus. The E2PROM and the CPU are also connected to each other via a peripheral circuit interconnect bus independent of the memory interconnect bus. During emulation, the emulation chip is connected to an in-circuit emulator via an emulator interconnect bus, and the memory interconnect bus is disconnected. However, the E2PROM controller allows electrical communication through the peripheral circuit interconnect bus and thereby accesses the E2PROM as one of peripheral circuits. Accordingly, it is possible to check out whether or not a reprogramming program stored in the E2PROM is running normally.Type: GrantFiled: December 14, 1998Date of Patent: May 29, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshiya Kai, Kazumi Yamada
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Patent number: 6240375Abstract: The number (Nc) of conductor regions and the number (Ncell(i)) of cells constituting each conductor region (ci) are calculated from the result of a configuration simulation. Each conductor region (ci) is judged whether or not the number (Ncell(i)) of cells thereof is less than a minimum cell count (Ncellmin) for recognition as an electrode or interconnect line. A conductor region (ci) judged that the number (Ncell(i)) of cells is not less than the minimum cell count (Ncellmin) is regarded as the electrode or interconnect line. A conductor region (ci) judged that the number (Ncell(i)) of cells is less than the minimum cell count (Ncellmin) is replaced with a dielectric positioned on a previously set one of the top, bottom, left-hand, right-hand, front and rear sides of the conductor region (ci).Type: GrantFiled: October 27, 1998Date of Patent: May 29, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Kenichiro Sonoda
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Patent number: 6240376Abstract: Methods of instrumenting synthesizable source code to enable debugging support akin to high-level language programming environments for gate-level simulation are provided. One method of facilitating gate level simulation includes generating cross-reference instrumentation data including instrumentation logic indicative of an execution status of at least one synthesizable register transfer level (RTL) source code statement. A gate-level netlist is synthesized from the source code. Evaluation of the instrumentation logic during simulation of the gate-level netlist facilitates simulation by indicating the execution status of a corresponding source code statement. One method results in a modified gatelevel netlist to generate instrumentation signals corresponding to synthesizable statements within the source code. This may be accomplished by modifying the source code or by generating the modified gate-level netlist as if the source code was modified during synthesis.Type: GrantFiled: July 31, 1998Date of Patent: May 29, 2001Assignee: Mentor Graphics CorporationInventors: Alain Raynaud, Luc M. Burgun
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Patent number: 6233540Abstract: The present invention is a design apparatus compiled on a computer environment for generating from a behavioral description of a system comprising at least one digital system part, an implementable description for said system, said behavioral description being represented on said computer environment as a first set of objects with a first set of relations therebetween, said implementable description being represented on said computer environment as a second set of objects with a second set of relations therebetween, said first and second set of objects being part of a design environment.Type: GrantFiled: March 13, 1998Date of Patent: May 15, 2001Assignee: Interuniversitair Micro-Elektronica CentrumInventors: Patrick Schaumont, Serge Vernalde, Johan Cockx
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Patent number: 6230119Abstract: A data processor is provided in which an embedded emulator communicates with a control emulation system using a serial communications link involving one pin of the data processor package.Type: GrantFiled: February 6, 1998Date of Patent: May 8, 2001Inventor: Patrick Michael Mitchell
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Patent number: 6230112Abstract: When a single performance or a plurality of antinomical performances are to be obtained, the best mode of a tire is designed under a given condition. A basic shape model using one block as a reference shape is obtained (100). An object function representing a tire performance evaluation physical amount, a constraint condition for restricting the tire shape, and a design variable which is an angle of a wall surface which determines the block shape are determined (102). Next, the design variable is varied continuously by &Dgr;ri to determine a modified shape model (104 to 108). A value of the object function of the modified shape model and a value of the constraint condition are calculated, and a sensitivity of the object function and a sensitivity of the constraint condition are determined (110, 112).Type: GrantFiled: August 27, 1998Date of Patent: May 8, 2001Assignee: Bridgestone CorporationInventor: Makoto Ishiyama
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Patent number: 6223145Abstract: An interactive interface for creating a search query for a corpus of machine-readable documents, each of which is associated with at least one category of a category hierarchy. The interactive interface includes a cone tree generation component, a query specification component, a begin search component, and a query generation component. The cone tree generation component generates and displays a cone tree representing the category hierarchy. The cone tree represents each category of the category hierarchy as a node having a selection object for indicating inclusion of the category in a one of a first group, and a second group. Each selection object is responsive to a cursor control device. The query specification component generates and displays a query specification object including a first group object and a second group object. Each group object is responsive to the cursor control device and indicates members of the group.Type: GrantFiled: November 25, 1998Date of Patent: April 24, 2001Assignee: Zerox CorporationInventor: Marti A. Hearst
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Patent number: 6219628Abstract: A system and method for configuring an instrument to perform measurement functions, wherein the instrument includes a programmable hardware element. A graphical program is first created, wherein the graphical program implements a measurement function. The graphical program may include a front panel and a block diagram. The method then generates a hardware description based on at least a portion of the graphical program. The hardware description describes a hardware implementation of the at least a portion of the graphical program. The method then configures the programmable hardware element in the instrument utilizing the hardware description to produce a configured hardware element. The configured hardware element thus implements a hardware implementation of the at least a portion of the graphical program. The instrument then acquires a signal from an external source, and the programmable hardware element in the instrument executes to perform the measurement function on the signal.Type: GrantFiled: August 18, 1997Date of Patent: April 17, 2001Assignee: National Instruments CorporationInventors: Jeffrey L. Kodosky, Hugo Andrade, Brian K. Odom, Cary P. Butler
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Patent number: 6208953Abstract: In a method for monitoring plants with mechanical components, measured values (xiT; xiu) are determined at predeterminable time intervals for a fixed set of parameters (xi). The measured values (xiT) which are determined for various working points during a modelling phase are used for the generation of a model for the operating behavior of the components. With the help of the model for the operating behavior at least one monitoring value (r; snu) is derived at predeterminable time intervals which is independent of the respective current working point. The temporal behavior of the monitoring value (r; snu) is used for estimating the wear in the components and/or for the detection of operating disturbances.Type: GrantFiled: January 14, 1998Date of Patent: March 27, 2001Assignee: Sulzer Innotec AGInventors: Janusz Milek, Heinz Guettinger
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Patent number: 6205413Abstract: Performance monitoring of network connections is an integral and necessary part of network operation, administration and management. The performance monitoring reflects the “goodness” of the communication system in supporting “high-level” data communication services to end-users. This is done by quantifying the perception of an end-user and using this quantification as a guideline for the capability of the network to provide communication services. The computer implemented process is a user-friendly, automated collection and tabulation of performance measurements that directly reflects the perception of an end-user on the capabilities of the underlying communications network. The disclosure is geared toward the “Web-centric” Internet world, but the method can be adapted to non-Internet communication systems.Type: GrantFiled: June 11, 1998Date of Patent: March 20, 2001Inventors: Chatschik Bisdikian, Kiyoshi Maruyama
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Patent number: 6202041Abstract: A versatile modelling for any standard power system component is disclosed, by which the component modules can be easily plugged into the network module to form a small perturbation state space model of the entire system irrespective of the complexity of the system. The state equation is available as explicitly a function of every parameter and the input and output can be any variable, thus providing insight into the physical nature by simple matrix manipulation.Type: GrantFiled: April 29, 1998Date of Patent: March 13, 2001Assignee: Hong Kong Polytechnic UniversityInventors: Chi Tong Tse, Chi Yung Chung
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Patent number: 6202044Abstract: A digital logic simulation/emulation system (20) operates in an engaged operating mode in which a digital-logic simulation process (22) transmits stimulation-control data to a hardware pod (32) for controlling stimulation of a digital logic circuit. In response to the stimulation-control data, the hardware pod (32) performs a stimulation-response cycle, and then sends response data from the digital logic circuit to the simulation process (22). The simulation process (22) and the hardware pod (32) may also operate in a disengaged operating mode in which each operates independently of the other without exchanging stimulation-control data or response data. Operation of the system (20) in the disengaged mode commences if a disengagement event occurs in the hardware pod (32). Operation of the system (20) in the disengaged mode terminates if the simulation process (22) sends stimulation-control data to the hardware pod (32), or if the hardware pod (32) sends response data to the simulation process (22).Type: GrantFiled: June 12, 1998Date of Patent: March 13, 2001Assignee: Simpod, Inc,Inventor: Yiftach Tzori
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Patent number: 6199030Abstract: Enhanced realism of a real-time simulator having multiple computer-controlled units results from making the units capable of reacting to only those other units that each of them can be aware of because of their spatial relationships to the unit. Awareness is based upon probabilities; it can persist after a relationship changes; and it can be influenced by a unit's designation of a target. Each unit selects a target based upon a score incorporating multiple aspects of its tactical situation, and can change targets when the situation changes. A unit selects a strategy in response to which of a set of tactical configurations exist between the unit and its target; the strategy can change short of completion when the configuration changes. A plan produces guidance commands from the high-level strategy. The guidance commands are converted into control settings for guiding the subject unit using a physics engine for simulating the physical dynamics of the unit.Type: GrantFiled: June 19, 1998Date of Patent: March 6, 2001Assignee: Microsoft CorporationInventor: Jeremy D. Stone
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Patent number: 6199031Abstract: An interface system for testing and verifying the design of an ASIC at different levels of abstraction, wherein the ASIC includes a logic entity and a processor entity. The system of the present invention is embodied as software which executes within a computer system. The software, when executed by the computer system, causes the computer system to implement a model of the ASIC, a simulator, and a test interface. The model of the ASIC is embodied in HDL (Hardware Description Language) and includes a logic entity and a processor entity. The simulator is adapted to test the model. The test interface interfaces the model with the simulator. The test interface includes a simulator portion and a model portion. The simulator portion is coupled to the simulator. The model portion is embodied in HDL and is coupled to both the logic entity and the processor entity. The model portion and the simulator portion are coupled to exchange information.Type: GrantFiled: August 31, 1998Date of Patent: March 6, 2001Assignee: VLSI Technology, Inc.Inventors: Pierre Yves Challier, Christelle Faucon, Jean Francois Duboc
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Patent number: 6199029Abstract: A topography simulation method using the Monte Carlo method is provided, which simulates the post-etching topography of a plasma-assisted etching process affected by different etching species such as the ion-assisted etching process. (a) A bulk- and/or sheath-plasma region is/are analyzed using a first random number, calculating a species energy of an incoming species. (b) A sort of the incoming species toward a minute surface region of a target material is selected using a second random number based on the species energy calculated in the step (a). (c) An absorption state of the incoming species with atoms of the target material on the minute surface region of the target material is selected using a third random number based on the species energy in the step (a) and the sort of the incoming species selected in the step (b).Type: GrantFiled: May 26, 1998Date of Patent: March 6, 2001Assignee: NEC CorporationInventor: Toshiyuki Ohta
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Patent number: 6195622Abstract: Building resource (e.g., Internet content) and attribute transition probability models and using such models for pre-fetching resources, editing resource link topology, building resource link topology templates, and collaborative filtering.Type: GrantFiled: January 15, 1998Date of Patent: February 27, 2001Assignee: Microsoft CorporationInventors: Steven J. Altschuler, Greg Ridgeway