Abstract: A process simulator and modeling methodology employs instantaneous property measures. The instantaneous measures of various polymer properties are tracked throughout the subject polymer manufacturing system and used to calculate respective property distribution functions. For example, property distributions of composition, molecular weight, stereoregularity and long chain branching are calculated, tracked in time and location throughout the manufacturing system, and used to model the polymer manufacturing system and polymerization process performed by the system. More specifically, the present invention calculates full distribution of polymer properties from the instantaneous property measures and tracked instantaneous property distributions. This enables accurate and computationally efficient modeling of the polymerization process and manufacturing system for carrying out the same.

Abstract: A computer program media embodies a program of instructions executable by a computer to perform method steps for simulating the dynamic response of a structural-acoustic system over a broad range of frequencies. The method includes the steps of wavenumber partioning a design of the structural-acoustic system into large-scale behavior and small-scale behavior; determining the large-scale behavior; and determining the small-scale behavior.

Abstract: A system for processing audio samples, which compensates for any error between a future state of the system after a delay through a network and the predicted value of the input at that future time. The system synchronizes the motion of an audio transport to the motion of an audio input which has been delayed in processing through the network.

Abstract: A current operating system such as Solaris.RTM. X86 is adapted to run a user program such as a Common Object File Format (COFF) executable program which was designed to run on a retrograde operating system such as an older version of UNIX.RTM.. The operating system is adapted to include an emulator module or COFF interpreter which emulates retrograde system calls that are unique to the COFF system. A Local Descriptor Table (LDT) which is constructed for the COFF program includes a main system call gate and an alternate system call gate that initially both point to a system call entry point in the operating system kernel. Prior to running a COFF program, the main system call gate is revectored to point to the COFF interpreter, such that all system calls generated by the COFF program are directed to the COFF interpreter. The COFF interpreter redirects current system calls which are compatible with the current operating system to the kernel via the alternate call gate.

Abstract: A method of designing an integrated circuit employs hardware testing rule checking so as to ensure hardware testability and to ensure that automated test program generation will succeed when the design cycle reaches that stage. The method calls for, first, receiving a proposed logic design defined at a functional or behavioral level; second, defining a test bench for simulating operation of the logic design, the test bench including at least one input vector for stimulating the logic design for verifying the operation of the logic design; receiving a predetermined set of one or more hardware testing rules associated with a target tester; simulating operation of the logic design using the test bench; and, prior to releasing the logic design for logic synthesis, checking the simulation for compliance with the hardware testing rule set. Preliminary checking of the design and test bench prior to synthesis can avoid costly corrections later in connection with test program generation.

Abstract: A system and a method for designing an accessory are disclosed. Upon selection by a user of a commodity including an accessory such as a necklace, a pendant, a finger ring, an earring or a bracelet which he/she wants to design, a multiplicity of photographic images of various types of parts making up the particular accessory constituting the commodity are displayed in order to enable the user to design the accessory by himself/herself. The user repeats the simulation of selecting a preferred one of the multiplicity of parts of various types on display, moving the selected part to a specified area in the display screen and appropriately combining each part thus moved. The user thus decides to produce an accessory of his/her own originality to his/her liking.

Abstract: A method for designing pneumatic tires for rolling conditions employs a finite element tire model configured by an operator. A first set of variables is applied to the tire model and steady state footprint conditions resulting from such application of the variables to the tire model are compared against predetermined footprint constraints to determine if the steady state footprint conditions and the footprint constraints have converged. If they have not, the set of control variables is incremented and the comparison is undertaken again until the steady state footprint conditions in the footprint constraints have converged. The concept of the invention is presented with particular application to a determination of the abrasion energy dissipation or wear potential, cornering stiffness, and residual aligning torque.

Abstract: Amplitude of transmission error of tooth pair of a gear is obtained in relation to actual contact ratio (.epsilon..sub.r) which is an angular range (.theta..sub.r) of actual contact of the surfaces of the tooth pair divided by an angular pitch (.theta..sub.p) of the gear. The specifications and/or tooth surface modification of the gear is/are are determined so as to reduce the transmission error amplitude under non-load condition in which the actual contact ratio (.epsilon..sub.r) is 1.0. Alternatively, the specifications and/or tooth surface modifications is/are determined so as to increase an effective contact ratio (.epsilon..sub.n) which is an angular range (.theta..sub.n) divided by the angular pitch (.theta..sub.p), the angular range (.theta..sub.n) corresponding to a portion of a path of the tooth contact point in which an edge contact of the tooth pair does not take place at the tooth top or at the ends of the face width of the teeth.

Abstract: A computerized method and system for interactively simulating a plurality of telecommunications services operates in response to a user sending a message from his client computer across a data network to a server requesting to download on one of the service simulation programs. In response to the message from the client, the server provides the requested telecommunications service simulation program. The program provided by the server is downloaded and executed by the client. The downloaded program provides the user with an interaction experience representative of the selected one of the plurality of telecommunications services. This interaction experience may include additional communication between the service simulation program and the server. Additionally, the service simulation program provides guidance to the user in using and configuring both the service simulation program and, potentially, the actual telecommunications service to which the user has subscribed.

Abstract: A model of a physical object is constructed in a modeling system running on a computer system. The model includes model objects and constraints. The constraints on the model describe the relationship between the model objects. The modeling system constructs a graph representing the model. The graph has nodes representing the modeling objects and arcs representing the relationships between the model objects. The relationships are either directed or nondirected. The modeling system then identifies the set of cycles in the graph. The cycles have a subset of the nodes of the graph coupled by arcs representing nondirected relationships. The modeling system starts with a first cycle from the set of cycles and determines the set of programs that can be used to satisfy all of the relationships between the model objects represented by nodes in the first cycle.

Abstract: A computer system for modeling is disclosed, where the computer system has a storage device, first and second platforms, a portable persistent model, and first and second platform-dependent computerized modeling systems (CMS). Each platform is interfaced to the storage device and provides system-dependent services. The first platform has a first type of operating system and a first type of computer hardware including a first memory, and the second platform has a second type of operating system and a second type of computer hardware including a second memory. The model resides in the storage device in a platform-independent format and includes persistent component objects. The first CMS resides in the first platform memory and the second platform-dependent CMS resides in the second platform memory.

Abstract: A model predictive controller for a process control system which includes a real-time executive sequencer and an interactive modeler. The interactive modeler includes both a process model and an independent disturbance model. The process model represents the dynamic behavior of the physical process, while the disturbance model represents current and future deviations from the process model. The interactive modeler estimates current process states from the process model and input data received from the executive sequencer. The executive sequencer then projects a set of future process parameter values, which are sought to be controlled, over a predetermined control horizon. The interactive modeler then solves a set of equations as to how the physical process will react to control changes in order to determine an optimized set of control changes. As a result, the process control system will be able to accurately track a predetermined set-point profile in the most effective and cost efficient manner.

Abstract: A method and apparatus for emulating operation of a complex circuit within a system, thereby creating a virtual system, is achieved within a system that includes a central processing unit (CPU), system memory, at least one functional module, and an emulator that includes a circuit simulator, a virtual coupler, and an evaluation module. The circuit simulator simulates the functionality of the complex circuit, includes an individual system identifier, and is operably coupled to, and substantially controlled by, the at least one functional module. At system start-up, or at initiation of a simulation test, the system determines its configuration by obtaining the individual system identifiers of each system element. Because the circuit simulator has a system identifier, it is treated by the system as a real entity. As such, when the CPU requests the function of the complex circuit to be performed, the CPU provides its request to the at least one functional module.

Abstract: A system and method for modeling activities of people in an organization. The organization is modeled using definitions of processes performed by the organization, definitions of data elements generated by the entities performing the processes, and definitions of relationships between the data elements generated and the processes. Each relationship definition symbolizes a data element provided by a first one of the processes and required by a second one of the processes. In an example embodiment, the database is accessible to a server system, and a client system is coupled to the server system. Responsive to an input control signal at the client system, a request is sent to the server system for organization modeling data. The client system displays the organization modeling data, wherein processes are depicted as nodes on a graph and the data elements are depicted as directed edges connecting nodes. The system also models events that cause transitions between the processes.

Abstract: Disclosed is a method of designing a memory device that has substantially reduced bitline voltage offsets. The method includes providing a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The method also includes designing a six transistor core cell having a bitline and a complementary bitline, and designing a flipped six transistor core cell that has a flipped bitline and a flipped complementary bitline. Further, the method includes arranging a six transistor core cell followed by a flipped six transistor core cell along each of the multiple pairs of the global bitline and the global complementary bitline. Preferably, the bitline of the six transistor core cell is coupled with the flipped complementary bitline of the flipped six transistor core cell, and the complementary bitline of the six transistor core cell is coupled to the flipped bitline of the flipped six transistor core cell.

Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

Abstract: The present invention includes a modeling and testbench creation methodology which will allow a simulator to provide information regarding the state and direction of a bi-directional pad or pin. The present invention provides ATE tools all of the required data used to accurately and efficiently check for tester compatibility for which test patterns are extracted. In particular, the present invention includes a method of modeling a bi-directional I/O pad that includes the steps of providing a first signal in a first model; providing a second signal in a second model; and determining contention and direction of a resolved signal that is generated in response to at least one of the input and output signals. The first signal is a preferred output signal that is contained within an ASIC (first) model. The second signal is a preferred input signal that is contained within a testbench (second) model.

Abstract: The disclosed hardware and software co-simulator can execute two simulations effectively between two simulators each for executing simulation independently, by eliminating the idle times for waiting the execution end of the opposite simulator. The co-simulator is constructed in such a way that the time data generated at which the events transferred between a fist simulator and a second simulator occur can be extracted by analyzing the simulation data; and the expected occurrence times of the events to be transferred between the simulators are previously indicated to each simulator on the basis of the event occurrence time data.

Abstract: A method and data processing system for emulating a program are disclosed. According to the present invention, the data processing system runs under a first operating system and emulates the execution of a program under a second operating system within a second data processing system. The data processing system includes a memory which stores at least a portion of the first operating system and an emulator comprising a plurality of routines which each emulate an instruction utilized by the first operating system. The memory further includes a simulated mass storage data area which stores at least a portion of the program and a simulated main memory data area. The data processing system further includes a processor which executes instructions within the program under the first operating system by emulation. According to the present invention, the emulator accesses instructions of the program directly from the simulated mass storage data area to minimize emulation overhead.