Abstract: 3-d flash memory cells and methods of manufacture are described. The devices and methods recess a compound floating gate in between the silicon oxide slabs which reduces the quantum probability of electron tunneling between vertically adjacent storage cells. The devices and methods further include a high work function nanocrystalline metal in the compound floating gate. A polysilicon buffer layer forms a portion of the compound floating gate. The polysilicon buffer layer allows the high work function nanocrystalline metal to be selectively deposited. The polysilicon buffer layer further protects the high work function nanocrystalline metal from oxidation with the gate oxide subsequently formed on the other side.

Abstract: A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer on the first nitride semiconductor layer; a first electrode and a second electrode disposed on or above the first nitride semiconductor layer; a gate electrode above the first nitride semiconductor layer; and a gate insulating layer, the gate insulating layer including a silicon oxide film and an aluminum oxynitride film, the aluminum oxynitride film disposed between the first nitride semiconductor layer and the silicon oxide film, a first atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a first position in the aluminum oxynitride film being higher than a second atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a second position in the aluminum oxynitride film, and the second position being closer to the silicon oxide film than the first position.

Abstract: Some embodiments relate to an integrated circuit including a semiconductor substrate including a multi-voltage device region. A first pair of source/drain regions are spaced apart from one another by a first channel region. A dielectric layer is disposed over the first channel region. A barrier layer is disposed over the dielectric layer. A fully silicided gate is disposed over the first channel region and is vertically separated from the semiconductor substrate by a work function tuning layer. The work function tuning layer separates the fully silicided gate from the barrier layer.

Abstract: A memory device includes first electrode layers stacked in a first direction, a first semiconductor layer piercing the first electrode layers in a first direction, a first insulating film surrounding the first semiconductor layer, and a semiconductor base connected to the first semiconductor layer. The first insulating film includes a first film, a second film, and a third film provided in order in a second direction from the first semiconductor layer toward one of first electrode layers. Spacing in the first direction between the second film and the semiconductor base is wider than a film thickness of the third film in the second direction. A minimum width of an outer perimeter of the first semiconductor layer is substantially the same as a width of an outer perimeter at a portion of the first semiconductor layer piercing the most proximal first electrode layer.

Abstract: A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe.

Abstract: In an embodiment, a semiconductor device includes a semiconductor body having a field effect transistor device with an active region and an edge termination region that surrounds the active region on all sides. The active region includes a first serpentine trench in the semiconductor body, a first field plate in the first serpentine trench, a second serpentine trench in the semiconductor body, and a second field plate in the second serpentine trench. The first serpentine trench is separate and laterally spaced apart from the second serpentine trench.

Abstract: A method including forming hard mask patterns on a substrate; forming etch stop patterns surrounding the hard mask patterns; forming spacer patterns covering sidewalls of the etch stop patterns; removing the etch stop patterns; etching the substrate to form active and dummy fins; forming a block mask pattern layer surrounding the active and dummy fins and forming mask etch patterns on a top surface of the block mask pattern layer; etching the block mask pattern layer to form block mask patterns surrounding the active fins; etching the dummy fins; removing the block mask patterns surrounding the active fins; and depositing a device isolation film on the substrate such that the device isolation film is not in contact with the upper portions of the active fins, wherein a spacing distance between the active fin and the dummy fin is greater than an active fin spacing distance between the active fins.

Abstract: A light-emitting semiconductor chip comprises: a radiation-transmissive substrate, an epitaxially grown semiconductor layer sequence on a main surface of the substrate, a first contact and a second contact on a contact surface of the semiconductor layer sequence facing away from the substrate for electrical and mechanical contacting of the semiconductor chip, a transparent, electrically conductive layer which is arranged on the contact side and is electrically connected to the first contact.

Abstract: A device includes a fin structure, a dielectric layer, a gate a spacer, and an epitaxy structure. The dielectric layer is over the fin structure. The gate is over the dielectric layer. The spacer is on a sidewall of the gate. The spacer has a thickness along a direction parallel to a longitudinal axis of the fin structure, and a distance along the direction from an outer sidewall of the spacer to an end surface of the fin structure is greater than the thickness of the spacer. The epitaxy structure is in contact with the fin structure.

Abstract: The present invention provides a manufacturing method of a TFT substrate and structure. The manufacturing method of the TFT substrate deposit a black photoresist on the second passivation layer (PV2) and patterning to form a main integrated photoresist spacer (61), a sub-photoresist spacer (62) and a black matrix (63), then depositing a transparent conductive film on the integrated main photoresist spacer, the sub-photoresist spacer and the black matrix and patterning to form a pixel electrode (71) and a common electrode (72).

Abstract: Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a first die and a second die bonded to the first die. The first die includes a first integrated circuit region and a first seal ring region around the first integrated circuit region, and has a first alignment mark within the first integrated circuit region. The second die includes a second integrated circuit region and a second seal ring region around the second integrated circuit region, and has a second alignment mark within the second seal ring region and corresponding to the first alignment mark.

Abstract: A lighting apparatus using an organic light-emitting diode (OLED) of the present disclosure is characterized in that an inner light extraction layer is provided between a substrate and an OLED, and concurrently, a multi-buffer layer, of which a refractive index is gradually changed, is formed on the inner light extraction layer. According to the present disclosure, light extraction due to scattering may be improved by applying the inner light extraction layer, and a waveguide mode may be extracted as light by applying the multi-buffer layer, thereby improving luminous efficiency.

Abstract: A light emitting device package according to an embodiment includes: a body including first and second openings passing through an upper surface of the body and a lower surface of the body; a light emitting device disposed on the body and including first and second bonding parts; and first and second conductive layers disposed under the body and electrically connected to the first and second bonding parts, respectively, wherein each of the first and second bonding parts includes a protrusion portion protruding and extending in a downwards direction within the first and second openings, respectively.

Abstract: Each of a plurality of the light-emitting units (140) includes a first electrode (110), an organic layer (120), and a second electrode (130). The first electrode (110) is light-transmitting, and the second electrode (130) is light-reflective. The organic layer (120) is located between the first electrode (110) and the second electrode (130). The light-transmitting regions (104 and 106) are located between the plurality of light-emitting units (140). A sealing member (170) covers the plurality of light-emitting units (140) and the light-transmitting regions (104 and 106). The sealing member (170) is fixed directly or through an insulating layer (174) to at least one of a structure (for example, the second electrode 130) formed on a substrate (100), and the substrate (100). In addition, a haze value of the light-emitting device (10) is equal to or less than 2.0%, preferably equal to or less than 1.4%.

Abstract: A backside illuminated image sensor includes pixel regions disposed in a substrate, an anti-reflective layer disposed on a backside surface of the substrate, a light-blocking pattern disposed on the anti-reflective layer and having openings corresponding to the pixel regions, a color filter layer disposed on the light-blocking pattern, and a micro lens array disposed on the color filter layer, wherein the light-blocking pattern has a width decreasing toward the backside surface of the substrate.

Abstract: The invention discloses a backlight apparatus including a wavelength-converting device and a light source. The wavelength-converting device includes a transparent upper barrier film, a transparent lower barrier film, a spacer layer, a filling material and a plurality of quantum dots. The spacer layer is bonded between the transparent upper barrier film and the transparent lower barrier film, and has a plurality of hollowed regions. The filling material covers the plurality of hollowed regions. The plurality of quantum dots are uniformly distributed in the filling material covering each hollowed region. The light source includes a circuit board and a plurality of semiconductor light-emitting device. The circuit board is disposed beneath the transparent lower barrier film. Each hollowed region corresponds to at least one semiconductor light-emitting device. Each semiconductor light-emitting device is electrically bonded on the circuit board, and locates beneath the corresponding hollowed region.

Abstract: A charge-compensation semiconductor device includes a source metallization spaced apart from a gate metallization, and a semiconductor body including opposing first and second sides, a drift region, a plurality of body regions adjacent the first side and each forming a respective first pn-junction with the drift region, and a plurality of compensation regions arranged between the second side and the body regions. Each compensation region forms a respective further pn-junction with the drift region. A plurality of gate electrodes in Ohmic connection with the gate metallization is arranged adjacent the first side and separated from the body regions and the drift region by a dielectric region. A resistive current path is formed between one of the gate electrodes and a first one of the compensation regions, or between the first one of the compensation regions and a further metallization spaced apart from the source metallization and the gate metallization.

Abstract: A phosphor containing particle including a core portion which is a particulate matter of resin including a constitutional unit derived from an ionic liquid with a semiconductor nanoparticle phosphor dispersed therein and a shell portion which is a matter in a form of a layer of resin which includes a constitutional unit derived from an ionic liquid and coats at least a portion of the core portion, and a phosphor containing particle including a particulate matter of resin including a constitutional unit derived from an ionic liquid with a semiconductor nanoparticle phosphor dispersed therein and a metal oxide layer coating at least a portion of the particulate matter of resin. A light emitting device including a light source and a wavelength converter in which phosphor containing particles are dispersed in a translucent medium, and a phosphor containing sheet in which phosphor containing particles are dispersed in a sheet-shaped translucent medium.

Abstract: A rimless display device and a preparation method thereof, the rimless display device comprises a flexible substrate formed on a rigid base plate (1), the flexible substrate is provided with a display region (2) having an organic light-emitting layer arranged therein and a non-display region (3), wherein, after a part of the rigid base plate at a location corresponding to the non-display region (3) is removed, the non-display region (3) of the flexible substrate is fixed on a lateral surface or a rear surface of the display device after the non-display region (3) is folded. This rimless display device can achieve a real rimless display screen body, thereby further increasing the screen proportion and greatly improving the view effect.

Abstract: A package structure includes a semiconductor substrate, conductive pads, and conductive vias. The conductive pads are located on and electrically connected to the semiconductor substrate, and each have a testing region and a contact region comprising a core contact region and a buffer contact region, wherein along one direction, the conductive pads each have a maximum length less than a sum of a maximum length of the testing region and a maximum length of the buffer contact region. The conductive vias are respectively located on the core contact regions of the conductive pads.