Abstract: A semiconductor device includes an electronic component, a package, a substrate and a plurality of first conductors and second conductors. The package is over the electronic component. T substrate is between the electronic component and the package. The substrate includes a first portion covered by the package, and a second portion protruding out of an edge of the package and uncovered by the package. The first conductors and second conductors are between and electrically connected to the electronic component and the substrate. A width of a second conductor of the plurality of second conductors is larger than a width of a first conductor of the plurality of first conductors, the first conductors are disposed between the second portion of the substrate and the electronic component, and the second conductors are disposed between the first portion of the substrate and the electronic component.

Abstract: An IGBT module with an improved heat dissipation structure includes a layer of IGBT chips, a bonding layer, a thick copper layer, a polymer composite layer, a thermal spray layer, and a heat dissipation layer. The thermal spray layer is disposed on the heat dissipation layer. The polymer composite layer is disposed on the thermal spray layer. The thick copper layer is disposed on the polymer composite layer. The bonding layer is disposed on the thick copper layer. The layer of IGBT chips is disposed on the bonding layer.

Abstract: An assembly is provided including one or more semiconductor dice attached on a substrate, the semiconductor die provided with electrically-conductive stud bumps opposite the substrate. The stud bumps embedded in a molding compound molded thereon are exposed to grinding thus leveling the molding compound to expose the distal ends of the stud bumps at a surface of the molding compound. Recessed electrically-conductive lines extending over said surface of the molding compound with electrically-conductive lands over the distal ends of the stud bumps. A further molding compound is provided to cover the recessed electrically-conductive lines and surrounding the electrically-conductive lands.

Abstract: A display device enables transparent display at increased transparency and double-sided emission display, thereby being capable of improving aperture ratio during emission. The display device includes a transmission part having a configuration capable of selectively achieving a transmission function and a double-sided emission function.

Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, a common source extension structure including a first semiconductor layer having an n-type conductivity and a gate insulating layer between the substrate and the channel structures, a plurality of gate electrodes on the common source extension structure and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension structure and including a second semiconductor layer having an n-type conductivity. An upper portion of the common source extension structure has a first width, and a lower portion of the common source extension structure has a second width smaller than the first width.

Abstract: A display device includes a display panel having a first emission region and a second emission region that is distinct from and mutually exclusive to the first emission region. The first emission region is surrounded by, and is in contact with, the second emission region on all edges of the first emission region. The display panel includes a plurality of light emitters arranged in the first emission region and the second emission region. Respective light emitters of the plurality of light emitters are configured to emit light. The first emission region has a first density of light emitters. The second emission region has a second density of light emitters that is less than the first density.

Abstract: An information handling system includes an organic light emitting diode layer, an optically clear adhesive layer, and a flexible glass substrate. A surface film includes a self-healing polymer layer, the self-healing polymer layer including a self-healing polymer.

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

Abstract: Aspects of the disclosure provide a semiconductor apparatus that comprises a first field-effect transistor (FET) formed on a substrate and comprising a first gate, a second FET stacked on the first FET along a direction substantially perpendicular to the substrate and comprising a second gate. The semiconductor apparatus also comprises a first routing track and a second routing track electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along said direction. The semiconductor apparatus also comprises a first conductive trace configured to conductively couple the first gate of the first FET to the first routing track, and a second conductive trace configured to conductively couple the second gate of the second FET to the second routing track.

Abstract: An optoelectronic semiconductor chip includes a contact layer that impresses current directly into a first semiconductor region present in direct contact with a current web, the first semiconductor region is an n-side and a second semiconductor region is a p-side of a semiconductor layer sequence, and a second mirror layer is applied directly to a second semiconductor region, a plurality of contact fields and isolator fields are arranged alternately along a longitudinal direction of the current web, in the contact fields, the contact layer is in direct contact with the current web, and the isolator fields are free of the contact layer, and a first mirror layer is located between the current web and the first semiconductor region.

Abstract: A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure includes a n-type work function metal layer overlying the first high-k dielectric layer. The n-type work function metal layer includes a TiAl (titanium aluminum) alloy, in which an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3. The semiconductor device further includes a p-type gate structure over a second semiconductor fin, in which the p-type gate structure includes a p-type work function metal layer overlying the second high-k dielectric layer. The p-type work function metal layer includes titanium nitride (TiN), in which an atom ratio of Ti to N (nitrogen) is in a range substantially from 1:0.9 to 1:1.1.

Abstract: A display apparatus including a substrate having an active area and a sealing area surrounding the active area; a display unit disposed on the active area of the substrate and including a plurality of organic light-emitting devices; and a sealing member including a first portion, a second portion, and a third portion, the third portion disposed between the first portion and the second portion and connecting the first portion to the second portion.

Abstract: A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure is fluorine incorporated and includes a n-type work function metal layer overlying the first high-k dielectric layer. The n-type work function metal layer includes a TiAl (titanium aluminum) alloy, in which an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3. The semiconductor device further includes a p-type gate structure over a second semiconductor fin, in which the p-type gate structure is fluorine incorporated includes a p-type work function metal layer overlying the second high-k dielectric layer. The p-type work function metal layer includes titanium nitride (TiN), in which an atom ratio of Ti to N (nitrogen) is in a range substantially from 1:0.9 to 1:1.1.

Abstract: A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

Abstract: A light emitting device can include a layered perovskite, thereby determining the color of emission of the device.

Abstract: [Object] To provide a semiconductor protective film capable of suppressing a warpage of a semiconductor chip without impairing productivity and reliability, a semiconductor device including this, and a composite sheet. [Solving Means] A semiconductor protective film 10 according to an embodiment of the present invention includes a protective layer 11 formed of a non-conductive inorganic material and an adhesive layer 12 provided on one surface of the protective layer 11. The protective layer 11 includes at least a vitreous material and is typically formed of plate glass. Accordingly, a warpage of a semiconductor element as a protection target can be suppressed effectively.

Abstract: A quantum dot light-emitting diode and a display apparatus comprising the quantum dot light-emitting diode are provided. The quantum dot light-emitting diode comprises an anode, a hole injecting layer, a hole transporting layer, a quantum dot light-emitting layer, an electron transporting layer and a cathode from bottom to top, wherein the materials of the quantum dot light-emitting layer contain quantum dots and CuSCN nano-particles. By blending quantum dots and CuSCN nano-particles into a membrane to prepare a quantum dot light-emitting layer, a hole trap state on the surface of the quantum dots is passivated, and the transporting effect of a hole is improved, so that the injection of holes in the quantum dot light-emitting diode and that of electrons achieve balance, and thus the light-emitting efficiency and stability are improved.

Abstract: Techniques are disclosed for forming high mobility NMOS fin-based transistors having an indium-rich channel region electrically isolated from the sub-fin by an aluminum-containing layer. The aluminum aluminum-containing layer may be provisioned within an indium-containing layer that includes the indium-rich channel region, or may be provisioned between the indium-containing layer and the sub-fin. The indium concentration of the indium-containing layer may be graded from an indium-poor concentration near the aluminum-containing barrier layer to an indium-rich concentration at the indium-rich channel layer. The indium-rich channel layer is at or otherwise proximate to the top of the fin, according to some example embodiments. The grading can be intentional and/or due to the effect of reorganization of atoms at the interface of indium-rich channel layer and the aluminum-containing barrier layer. Numerous variations and embodiments will be appreciated in light of this disclosure.

Abstract: A GaAs-based compound semiconductor crystal includes a straight body portion having a cylindrical shape, wherein the straight body portion has a diameter of more than or equal to 110 mm and has a length of more than or equal to 100 mm and less than or equal to 400 mm, and the straight body portion has a first end surface and a second end surface having a higher specific resistance than a specific resistance of the first end surface, and a ratio R20/R10 of a specific resistance R20 at the second end surface side to a specific resistance R10 at the first end surface side is more than or equal to 1 and less than or equal to 2.